Loading drivers/gpu/drm/radeon/cik_reg.h +3 −0 Original line number Diff line number Diff line Loading @@ -24,6 +24,9 @@ #ifndef __CIK_REG_H__ #define __CIK_REG_H__ #define CIK_DIDT_IND_INDEX 0xca00 #define CIK_DIDT_IND_DATA 0xca04 #define CIK_DC_GPIO_HPD_MASK 0x65b0 #define CIK_DC_GPIO_HPD_A 0x65b4 #define CIK_DC_GPIO_HPD_EN 0x65b8 Loading drivers/gpu/drm/radeon/radeon.h +18 −0 Original line number Diff line number Diff line Loading @@ -2141,6 +2141,8 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v); #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) #define WREG32_P(reg, val, mask) \ do { \ uint32_t tmp_ = RREG32(reg); \ Loading Loading @@ -2272,6 +2274,22 @@ static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) WREG32(R600_UVD_CTX_DATA, (v)); } static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) { u32 r; WREG32(CIK_DIDT_IND_INDEX, (reg)); r = RREG32(CIK_DIDT_IND_DATA); return r; } static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) { WREG32(CIK_DIDT_IND_INDEX, (reg)); WREG32(CIK_DIDT_IND_DATA, (v)); } void r100_pll_errata_after_index(struct radeon_device *rdev); Loading Loading
drivers/gpu/drm/radeon/cik_reg.h +3 −0 Original line number Diff line number Diff line Loading @@ -24,6 +24,9 @@ #ifndef __CIK_REG_H__ #define __CIK_REG_H__ #define CIK_DIDT_IND_INDEX 0xca00 #define CIK_DIDT_IND_DATA 0xca04 #define CIK_DC_GPIO_HPD_MASK 0x65b0 #define CIK_DC_GPIO_HPD_A 0x65b4 #define CIK_DC_GPIO_HPD_EN 0x65b8 Loading
drivers/gpu/drm/radeon/radeon.h +18 −0 Original line number Diff line number Diff line Loading @@ -2141,6 +2141,8 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v); #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) #define WREG32_P(reg, val, mask) \ do { \ uint32_t tmp_ = RREG32(reg); \ Loading Loading @@ -2272,6 +2274,22 @@ static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) WREG32(R600_UVD_CTX_DATA, (v)); } static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) { u32 r; WREG32(CIK_DIDT_IND_INDEX, (reg)); r = RREG32(CIK_DIDT_IND_DATA); return r; } static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) { WREG32(CIK_DIDT_IND_INDEX, (reg)); WREG32(CIK_DIDT_IND_DATA, (v)); } void r100_pll_errata_after_index(struct radeon_device *rdev); Loading