Commit 1da37801 authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher
Browse files

drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED 



[Why]

DCN2 and DSC are stable enough to be build by default. So drop the flags.

[How]

Remove them using the unifdef tool. The following commands were executed
in sequence:

$ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';'
$ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';'

In addition:

* Remove from kconfig, and replace any dependencies with DCN1_0.
* Remove from any makefiles.
* Fix and cleanup NV defninitions in dal_asic_id.h
* Expand DCN1 ifdef to include DCN2 code in the following files:
    * clk_mgr/clk_mgr.c: dc_clk_mgr_create()
    * core/dc_resources.c: dc_create_resource_pool()
    * dce/dce_dmcu.c: dcn20_*lock_phy()
    * dce/dce_dmcu.c: dcn20_funcs
    * dce/dce_dmcu.c: dcn20_dmcu_create()
    * gpio/hw_factory.c: dal_hw_factory_init()
    * gpio/hw_translate.c: dal_hw_translate_init()

Signed-off-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3a2ce8d6

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+0 −4
Original line number Diff line number Diff line
@@ -1527,7 +1527,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) 
		}



parse_soc_bounding_box:

#ifdef CONFIG_DRM_AMD_DC_DCN2_0

		/*

		 * soc bounding box info is not integrated in disocovery table,

		 * we always need to parse it from gpu info firmware.
@@ -1538,7 +1537,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) 
									le32_to_cpu(hdr->header.ucode_array_offset_bytes));

			adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;

		}

#endif

		break;

	}

	default:
@@ -2602,8 +2600,6 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) 
	case CHIP_VEGA20:

#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	case CHIP_RAVEN:

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_NAVI12:

drivers/gpu/drm/amd/display/Kconfig

+1 −12
Original line number Diff line number Diff line
@@ -15,21 +15,11 @@ config DRM_AMD_DC 
config DRM_AMD_DC_DCN1_0

	def_bool n

	help

	  RV family support for display engine



config DRM_AMD_DC_DCN2_0

	bool "DCN 2.0 family"

	default y

	depends on DRM_AMD_DC && X86

	depends on DRM_AMD_DC_DCN1_0

	help

	  Choose this option if you want to have

	  Navi support for display engine

	  RV and NV family support for display engine



config DRM_AMD_DC_DCN2_1

	bool "DCN 2.1 family"

	depends on DRM_AMD_DC && X86

	depends on DRM_AMD_DC_DCN2_0

	help

	  Choose this option if you want to have

	  Renoir support for display engine
@@ -39,7 +29,6 @@ config DRM_AMD_DC_DSC_SUPPORT 
	default y

	depends on DRM_AMD_DC && X86

	depends on DRM_AMD_DC_DCN1_0

	depends on DRM_AMD_DC_DCN2_0

	help

	  Choose this option if you want to have

	  Dynamic Stream Compression support

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+0 −12
Original line number Diff line number Diff line
@@ -942,9 +942,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) 


	init_data.flags.power_down_display_on_boot = true;



#ifdef CONFIG_DRM_AMD_DC_DCN2_0

	init_data.soc_bounding_box = adev->dm.soc_bounding_box;

#endif



	/* Display Core create. */

	adev->dm.dc = dc_create(&init_data);
@@ -2755,11 +2753,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 
		break;

#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	case CHIP_RAVEN:

#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

	case CHIP_NAVI12:

	case CHIP_NAVI10:

	case CHIP_NAVI14:

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN2_1)

	case CHIP_RENOIR:

#endif
@@ -2915,7 +2911,6 @@ static int dm_early_init(void *handle) 
		adev->mode_info.num_dig = 4;

		break;

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

	case CHIP_NAVI10:

	case CHIP_NAVI12:

		adev->mode_info.num_crtc = 6;
@@ -2927,7 +2922,6 @@ static int dm_early_init(void *handle) 
		adev->mode_info.num_hpd = 5;

		adev->mode_info.num_dig = 5;

		break;

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN2_1)

	case CHIP_RENOIR:

		adev->mode_info.num_crtc = 4;
@@ -3227,11 +3221,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, 
	if (adev->asic_type == CHIP_VEGA10 ||

	    adev->asic_type == CHIP_VEGA12 ||

	    adev->asic_type == CHIP_VEGA20 ||

#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

	    adev->asic_type == CHIP_NAVI10 ||

	    adev->asic_type == CHIP_NAVI14 ||

	    adev->asic_type == CHIP_NAVI12 ||

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN2_1)

	    adev->asic_type == CHIP_RENOIR ||

#endif
@@ -3940,10 +3932,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 
	bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;

	int mode_refresh;

	int preferred_refresh = 0;

#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT

	struct dsc_dec_dpcd_caps dsc_caps;

	uint32_t link_bandwidth_kbps;

#endif



	struct dc_sink *sink = NULL;

	if (aconnector == NULL) {
@@ -4018,7 +4008,6 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 
		fill_stream_properties_from_drm_display_mode(stream,

			&mode, &aconnector->base, con_state, old_stream);



#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT

	stream->timing.flags.DSC = 0;



	if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
@@ -4037,7 +4026,6 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 
						  &stream->timing.dsc_cfg))

				stream->timing.flags.DSC = 1;

	}

#endif



	update_stream_scaling_settings(&mode, dm_state, stream);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

+0 −2
Original line number Diff line number Diff line
@@ -287,7 +287,6 @@ struct amdgpu_display_manager { 


	const struct firmware *fw_dmcu;

	uint32_t dmcu_fw_version;

#ifdef CONFIG_DRM_AMD_DC_DCN2_0

	/**

	 * @soc_bounding_box:

	 *
@@ -295,7 +294,6 @@ struct amdgpu_display_manager { 
	 * available in FW

	 */

	const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;

#endif

};



struct amdgpu_dm_connector {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

+0 −2
Original line number Diff line number Diff line
@@ -511,7 +511,6 @@ bool dm_helpers_submit_i2c( 


	return result;

}

#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT

bool dm_helpers_dp_write_dsc_enable(

		struct dc_context *ctx,

		const struct dc_stream_state *stream,
@@ -522,7 +521,6 @@ bool dm_helpers_dp_write_dsc_enable( 


	return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1);

}

#endif



bool dm_helpers_is_dp_sink_present(struct dc_link *link)

{