Commit 1eee6bb9 authored by Stanimir Varbanov's avatar Stanimir Varbanov
Browse files

venus: firmware: Correct assertion of reset bit on remote processor



Currently we use read/write_relaxed in combination with mb() to assert
reset. This looks wrong because mb() after write_relaxed() will not
order correctly load-update-store sequence. Correct this by use
readl/writel which include memory barriers.

Signed-off-by: default avatarStanimir Varbanov <stanimir.varbanov@linaro.org>
parent a837e516
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+4 −6
Original line number Diff line number Diff line
@@ -181,17 +181,15 @@ static int venus_shutdown_no_tz(struct venus_core *core)

	if (IS_V6(core)) {
		/* Assert the reset to XTSS */
		reg = readl_relaxed(wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);
		reg = readl(wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);
		reg |= WRAPPER_XTSS_SW_RESET_BIT;
		writel_relaxed(reg, wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);
		writel(reg, wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);
	} else {
		/* Assert the reset to ARM9 */
		reg = readl_relaxed(wrapper_base + WRAPPER_A9SS_SW_RESET);
		reg = readl(wrapper_base + WRAPPER_A9SS_SW_RESET);
		reg |= WRAPPER_A9SS_SW_RESET_BIT;
		writel_relaxed(reg, wrapper_base + WRAPPER_A9SS_SW_RESET);
		writel(reg, wrapper_base + WRAPPER_A9SS_SW_RESET);
	}
	/* Make sure reset is asserted before the mapping is removed */
	mb();

	iommu = core->fw.iommu_domain;