Commit 1f9986b2 authored by Sam Shih's avatar Sam Shih Committed by Matthias Brugger
Browse files

arm64: dts: mediatek: add clock support for mt7986a 



Add clock controller nodes, include 40M clock source, topckgen,
infracfg, apmixedsys and ethernet subsystem.

Signed-off-by: default avatarSam Shih <sam.shih@mediatek.com>
Link: https://lore.kernel.org/r/20220119123624.10043-2-sam.shih@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 994a71a3

arch/arm64/boot/dts/mediatek/mt7986a.dtsi

+63 −5
Original line number Diff line number Diff line
@@ -6,16 +6,18 @@ 


#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/mt7986-clk.h>



/ {

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	system_clk: dummy40m {

	clk40m: oscillator@0 {

		compatible = "fixed-clock";

		clock-frequency = <40000000>;

		#clock-cells = <0>;

		clock-output-names = "clkxtal";

	};



	cpus {
@@ -98,6 +100,18 @@ gic: interrupt-controller@c000000 { 
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		};



		infracfg: infracfg@10001000 {

			compatible = "mediatek,mt7986-infracfg", "syscon";

			reg = <0 0x10001000 0 0x1000>;

			#clock-cells = <1>;

		};



		topckgen: topckgen@1001b000 {

			compatible = "mediatek,mt7986-topckgen", "syscon";

			reg = <0 0x1001B000 0 0x1000>;

			#clock-cells = <1>;

		};



		watchdog: watchdog@1001c000 {

			compatible = "mediatek,mt7986-wdt",

				     "mediatek,mt6589-wdt";
@@ -107,6 +121,12 @@ watchdog: watchdog@1001c000 { 
			status = "disabled";

		};



		apmixedsys: apmixedsys@1001e000 {

			compatible = "mediatek,mt7986-apmixedsys";

			reg = <0 0x1001E000 0 0x1000>;

			#clock-cells = <1>;

		};



		pio: pinctrl@1001f000 {

			compatible = "mediatek,mt7986a-pinctrl";

			reg = <0 0x1001f000 0 0x1000>,
@@ -128,11 +148,25 @@ pio: pinctrl@1001f000 { 
			#interrupt-cells = <2>;

		};



		sgmiisys0: syscon@10060000 {

			compatible = "mediatek,mt7986-sgmiisys_0",

				     "syscon";

			reg = <0 0x10060000 0 0x1000>;

			#clock-cells = <1>;

		};



		sgmiisys1: syscon@10070000 {

			compatible = "mediatek,mt7986-sgmiisys_1",

				     "syscon";

			reg = <0 0x10070000 0 0x1000>;

			#clock-cells = <1>;

		};



		trng: trng@1020f000 {

			compatible = "mediatek,mt7986-rng",

				     "mediatek,mt7623-rng";

			reg = <0 0x1020f000 0 0x100>;

			clocks = <&system_clk>;

			clocks = <&infracfg CLK_INFRA_TRNG_CK>;

			clock-names = "rng";

			status = "disabled";

		};
@@ -142,7 +176,13 @@ uart0: serial@11002000 { 
				     "mediatek,mt6577-uart";

			reg = <0 0x11002000 0 0x400>;

			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&system_clk>;

			clocks = <&infracfg CLK_INFRA_UART0_SEL>,

				 <&infracfg CLK_INFRA_UART0_CK>;

			clock-names = "baud", "bus";

			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,

					  <&infracfg CLK_INFRA_UART0_SEL>;

			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,

						 <&topckgen CLK_TOP_UART_SEL>;

			status = "disabled";

		};
@@ -151,7 +191,11 @@ uart1: serial@11003000 { 
				     "mediatek,mt6577-uart";

			reg = <0 0x11003000 0 0x400>;

			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&system_clk>;

			clocks = <&infracfg CLK_INFRA_UART1_SEL>,

				 <&infracfg CLK_INFRA_UART1_CK>;

			clock-names = "baud", "bus";

			assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;

			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;

			status = "disabled";

		};
@@ -160,10 +204,24 @@ uart2: serial@11004000 { 
				     "mediatek,mt6577-uart";

			reg = <0 0x11004000 0 0x400>;

			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&system_clk>;

			clocks = <&infracfg CLK_INFRA_UART2_SEL>,

				 <&infracfg CLK_INFRA_UART2_CK>;

			clock-names = "baud", "bus";

			assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;

			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;

			status = "disabled";

		};



		ethsys: syscon@15000000 {

			 #address-cells = <1>;

			 #size-cells = <1>;

			 compatible = "mediatek,mt7986-ethsys",

				      "syscon";

			 reg = <0 0x15000000 0 0x1000>;

			 #clock-cells = <1>;

			 #reset-cells = <1>;

		};



	};



};