Commit 1fae6dfe authored by Dave Airlie's avatar Dave Airlie
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Merge branch 'exynos-drm-next' of...

Merge branch 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next

   This pull request includes i80 interface support, module auto-loading
   ipp consolidation, and trivail fixups and cleanups.

Summary:
- Add i80 interface support. For this, we added some features to
  Exynos drm framework, which don't affect any other SoC and common
  framework because they are specific to Exynos drm.
- Add module auto-loading support. For this, sub drivers of Exynos drm
  exports their of match tables to userspace. This allows modules to be
  loaded automatically based on devicetree information
- Consolidate ipp driver. This patch just just includes cleanups and
  a littl bit refactoring codes.

If there is any problem, please kindly let me know.

* 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos: (38 commits)
  drm/exynos: g2d: let exynos_g2d_get_ver_ioctl fail
  drm/exynos: g2d: make ioctls more robust
  drm/exynos: hdmi: add null check for hdmiphy_port
  drm/exynos: control blending of mixer graphic layer 0
  drm/exynos: Add MODULE_DEVICE_TABLE entries for various components
  Subject: Revert "drm/exynos: remove MODULE_DEVICE_TABLE definitions"
  Subject: Revert "drm/exynos: fix module build error"
  drm/exynos/ipp: simplify ipp_find_driver
  drm/exynos/ipp: simplify ipp_create_id
  drm/exynos/ipp: remove redundant messages
  drm/exynos/ipp: simplify ipp_find_obj
  drm/exynos/ipp: remove useless registration checks
  drm/exynos/ipp: simplify memory check function
  drm/exynos/ipp: remove incorrect checks of list_first_entry result
  drm/exynos/ipp: remove temporary variable
  drm/exynos/ipp: correct address type
  drm/exynos/ipp: remove struct exynos_drm_ipp_private
  drm/exynos/ipp: remove unused field from exynos_drm_ipp_private
  drm/exynos/ipp: remove type casting
  drm/exynos: g2d: add exynos4212 as a compatible device.
  ...
parents 08d645c1 ef7ce055
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+3 −1
Original line number Original line Diff line number Diff line
Exynos MIPI DSI Master
Exynos MIPI DSI Master


Required properties:
Required properties:
  - compatible: "samsung,exynos4210-mipi-dsi"
  - compatible: value should be one of the following
		"samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
		"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
  - reg: physical base address and length of the registers set for the device
  - reg: physical base address and length of the registers set for the device
  - interrupts: should contain DSI interrupt
  - interrupts: should contain DSI interrupt
  - clocks: list of clock specifiers, must contain an entry for each required
  - clocks: list of clock specifiers, must contain an entry for each required
+3 −2
Original line number Original line Diff line number Diff line
@@ -4,8 +4,9 @@ Required properties:
- compatible: value should be one of the following:
- compatible: value should be one of the following:
	1) "samsung,exynos5-mixer" <DEPRECATED>
	1) "samsung,exynos5-mixer" <DEPRECATED>
	2) "samsung,exynos4210-mixer"
	2) "samsung,exynos4210-mixer"
	3) "samsung,exynos5250-mixer"
	3) "samsung,exynos4212-mixer"
	4) "samsung,exynos5420-mixer"
	4) "samsung,exynos5250-mixer"
	5) "samsung,exynos5420-mixer"


- reg: physical base address of the mixer and length of memory mapped
- reg: physical base address of the mixer and length of memory mapped
	region.
	region.
+28 −0
Original line number Original line Diff line number Diff line
@@ -44,6 +44,34 @@ Optional Properties:
- display-timings: timing settings for FIMD, as described in document [1].
- display-timings: timing settings for FIMD, as described in document [1].
		Can be used in case timings cannot be provided otherwise
		Can be used in case timings cannot be provided otherwise
		or to override timings provided by the panel.
		or to override timings provided by the panel.
- samsung,sysreg: handle to syscon used to control the system registers
- i80-if-timings: timing configuration for lcd i80 interface support.
  - cs-setup: clock cycles for the active period of address signal is enabled
              until chip select is enabled.
              If not specified, the default value(0) will be used.
  - wr-setup: clock cycles for the active period of CS signal is enabled until
              write signal is enabled.
              If not specified, the default value(0) will be used.
  - wr-active: clock cycles for the active period of CS is enabled.
               If not specified, the default value(1) will be used.
  - wr-hold: clock cycles for the active period of CS is disabled until write
             signal is disabled.
             If not specified, the default value(0) will be used.

  The parameters are defined as:

    VCLK(internal)  __|??????|_____|??????|_____|??????|_____|??????|_____|??
                      :            :            :            :            :
    Address Output  --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
                      | cs-setup+1 |            :            :            :
                      |<---------->|            :            :            :
    Chip Select     ???????????????|____________:____________:____________|??
                                   | wr-setup+1 |            | wr-hold+1  |
                                   |<---------->|            |<---------->|
    Write Enable    ????????????????????????????|____________|???????????????
                                                | wr-active+1|
                                                |<---------->|
    Video Data      ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--


The device node can contain 'port' child nodes according to the bindings defined
The device node can contain 'port' child nodes according to the bindings defined
in [2]. The following are properties specific to those nodes:
in [2]. The following are properties specific to those nodes:
+1 −0
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@@ -608,6 +608,7 @@ fimd: fimd@11c00000 {
		clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
		clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
		clock-names = "sclk_fimd", "fimd";
		clock-names = "sclk_fimd", "fimd";
		samsung,power-domain = <&pd_lcd0>;
		samsung,power-domain = <&pd_lcd0>;
		samsung,sysreg = <&sys_reg>;
		status = "disabled";
		status = "disabled";
	};
	};
};
};
+1 −0
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@@ -87,6 +87,7 @@ fimd@14400000 {
		reg = <0x14400000 0x40000>;
		reg = <0x14400000 0x40000>;
		interrupt-names = "fifo", "vsync", "lcd_sys";
		interrupt-names = "fifo", "vsync", "lcd_sys";
		interrupts = <18 4>, <18 5>, <18 6>;
		interrupts = <18 4>, <18 5>, <18 6>;
		samsung,sysreg = <&sysreg_system_controller>;
		status = "disabled";
		status = "disabled";
	};
	};


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