Merge branch 'msm-next-lumag-dpu' into msm-next-lumag (2470e932) · Commits · jan.koester / Linux

Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml

0 → 100644

+133 −0

Original line number	Diff line number	Diff line
		# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Qualcomm SM8550 Display DPU

		maintainers:
		- Neil Armstrong <neil.armstrong@linaro.org>

		$ref: /schemas/display/msm/dpu-common.yaml#

		properties:
		compatible:
		const: qcom,sm8550-dpu

		reg:
		items:
		- description: Address offset and size for mdp register set
		- description: Address offset and size for vbif register set

		reg-names:
		items:
		- const: mdp
		- const: vbif

		clocks:
		items:
		- description: Display AHB
		- description: Display hf axi
		- description: Display MDSS ahb
		- description: Display lut
		- description: Display core
		- description: Display vsync

		clock-names:
		items:
		- const: bus
		- const: nrt_bus
		- const: iface
		- const: lut
		- const: core
		- const: vsync

		required:
		- compatible
		- reg
		- reg-names
		- clocks
		- clock-names

		unevaluatedProperties: false

		examples:
		- \|
		#include <dt-bindings/clock/qcom,sm8550-dispcc.h>
		#include <dt-bindings/clock/qcom,sm8550-gcc.h>
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/power/qcom-rpmpd.h>

		display-controller@ae01000 {
		compatible = "qcom,sm8550-dpu";
		reg = <0x0ae01000 0x8f000>,
		<0x0aeb0000 0x2008>;
		reg-names = "mdp", "vbif";

		clocks = <&gcc GCC_DISP_AHB_CLK>,
		<&gcc GCC_DISP_HF_AXI_CLK>,
		<&dispcc DISP_CC_MDSS_AHB_CLK>,
		<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
		<&dispcc DISP_CC_MDSS_MDP_CLK>,
		<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
		clock-names = "bus",
		"nrt_bus",
		"iface",
		"lut",
		"core",
		"vsync";

		assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
		assigned-clock-rates = <19200000>;

		operating-points-v2 = <&mdp_opp_table>;
		power-domains = <&rpmhpd SM8550_MMCX>;

		interrupt-parent = <&mdss>;
		interrupts = <0>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		dpu_intf1_out: endpoint {
		remote-endpoint = <&dsi0_in>;
		};
		};

		port@1 {
		reg = <1>;
		dpu_intf2_out: endpoint {
		remote-endpoint = <&dsi1_in>;
		};
		};
		};

		mdp_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-200000000 {
		opp-hz = /bits/ 64 <200000000>;
		required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-325000000 {
		opp-hz = /bits/ 64 <325000000>;
		required-opps = <&rpmhpd_opp_svs>;
		};

		opp-375000000 {
		opp-hz = /bits/ 64 <375000000>;
		required-opps = <&rpmhpd_opp_svs_l1>;
		};

		opp-514000000 {
		opp-hz = /bits/ 64 <514000000>;
		required-opps = <&rpmhpd_opp_nom>;
		};
		};
		};
		...

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

+80 −217

Original line number	Diff line number	Diff line
		@@ -401,6 +401,47 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
		}
		}

		static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
		struct drm_plane *plane,
		struct dpu_crtc_mixer *mixer,
		u32 num_mixers,
		enum dpu_stage stage,
		struct dpu_format *format,
		uint64_t modifier,
		struct dpu_sw_pipe *pipe,
		unsigned int stage_idx,
		struct dpu_hw_stage_cfg *stage_cfg
		)
		{
		uint32_t lm_idx;
		enum dpu_sspp sspp_idx;
		struct drm_plane_state *state;

		sspp_idx = pipe->sspp->idx;

		state = plane->state;

		trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
		state, to_dpu_plane_state(state), stage_idx,
		format->base.pixel_format,
		modifier);

		DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n",
		crtc->base.id,
		stage,
		plane->base.id,
		sspp_idx - SSPP_NONE,
		state->fb ? state->fb->base.id : -1,
		pipe->multirect_index);

		stage_cfg->stage[stage][stage_idx] = sspp_idx;
		stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index;

		/* blend config update */
		for (lm_idx = 0; lm_idx < num_mixers; lm_idx++)
		mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, sspp_idx);
		}

		static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
		struct dpu_crtc dpu_crtc, struct dpu_crtc_mixer mixer,
		struct dpu_hw_stage_cfg *stage_cfg)
		@@ -413,15 +454,12 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
		struct dpu_format *format;
		struct dpu_hw_ctl *ctl = mixer->lm_ctl;

		uint32_t stage_idx, lm_idx;
		int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 };
		uint32_t lm_idx;
		bool bg_alpha_enable = false;
		DECLARE_BITMAP(fetch_active, SSPP_MAX);

		memset(fetch_active, 0, sizeof(fetch_active));
		drm_atomic_crtc_for_each_plane(plane, crtc) {
		enum dpu_sspp sspp_idx;

		state = plane->state;
		if (!state)
		continue;
		@@ -432,40 +470,30 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
		pstate = to_dpu_plane_state(state);
		fb = state->fb;

		sspp_idx = dpu_plane_pipe(plane);
		set_bit(sspp_idx, fetch_active);

		DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n",
		crtc->base.id,
		pstate->stage,
		plane->base.id,
		sspp_idx - SSPP_VIG0,
		state->fb ? state->fb->base.id : -1);

		format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));

		if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
		bg_alpha_enable = true;

		stage_idx = zpos_cnt[pstate->stage]++;
		stage_cfg->stage[pstate->stage][stage_idx] =
		sspp_idx;
		stage_cfg->multirect_index[pstate->stage][stage_idx] =
		pstate->multirect_index;
		set_bit(pstate->pipe.sspp->idx, fetch_active);
		_dpu_crtc_blend_setup_pipe(crtc, plane,
		mixer, cstate->num_mixers,
		pstate->stage,
		format, fb ? fb->modifier : 0,
		&pstate->pipe, 0, stage_cfg);

		trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
		state, pstate, stage_idx,
		sspp_idx - SSPP_VIG0,
		format->base.pixel_format,
		fb ? fb->modifier : 0);
		if (pstate->r_pipe.sspp) {
		set_bit(pstate->r_pipe.sspp->idx, fetch_active);
		_dpu_crtc_blend_setup_pipe(crtc, plane,
		mixer, cstate->num_mixers,
		pstate->stage,
		format, fb ? fb->modifier : 0,
		&pstate->r_pipe, 1, stage_cfg);
		}

		/* blend config update */
		for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
		_dpu_crtc_setup_blend_cfg(mixer + lm_idx,
		pstate, format);

		mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl,
		sspp_idx);
		_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);

		if (bg_alpha_enable && !format->alpha_enable)
		mixer[lm_idx].mixer_op_mode = 0;
		@@ -768,7 +796,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)

		/* stage config flush mask */
		ctl->ops.update_pending_flush_dspp(ctl,
		mixer[i].hw_dspp->idx);
		mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
		}
		}

		@@ -1134,18 +1162,14 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
		drm_crtc_vblank_on(crtc);
		}

		struct plane_state {
		struct dpu_plane_state *dpu_pstate;
		const struct drm_plane_state *drm_pstate;
		int stage;
		u32 pipe_id;
		};

		static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate)
		{
		struct drm_crtc *crtc = cstate->crtc;
		struct drm_encoder *encoder;

		if (cstate->self_refresh_active)
		return true;

		drm_for_each_encoder_mask (encoder, crtc->dev, cstate->encoder_mask) {
		if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_CMD) {
		return true;
		@@ -1162,151 +1186,46 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
		crtc);
		struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
		struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);
		struct plane_state *pstates;

		const struct drm_plane_state *pstate;
		struct drm_plane *plane;
		struct drm_display_mode *mode;

		int cnt = 0, rc = 0, mixer_width = 0, i, z_pos;
		int rc = 0;

		struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2];
		int multirect_count = 0;
		const struct drm_plane_state *pipe_staged[SSPP_MAX];
		int left_zpos_cnt = 0, right_zpos_cnt = 0;
		struct drm_rect crtc_rect = { 0 };
		bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);

		pstates = kzalloc(sizeof(pstates) DPU_STAGE_MAX * 4, GFP_KERNEL);
		if (!pstates)
		return -ENOMEM;

		if (!crtc_state->enable \|\| !crtc_state->active) {
		if (!crtc_state->enable \|\| !drm_atomic_crtc_effectively_active(crtc_state)) {
		DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n",
		crtc->base.id, crtc_state->enable,
		crtc_state->active);
		memset(&cstate->new_perf, 0, sizeof(cstate->new_perf));
		goto end;
		return 0;
		}

		mode = &crtc_state->adjusted_mode;
		DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name);

		/* force a full mode set if active state changed */
		if (crtc_state->active_changed)
		crtc_state->mode_changed = true;

		memset(pipe_staged, 0, sizeof(pipe_staged));

		if (cstate->num_mixers) {
		mixer_width = mode->hdisplay / cstate->num_mixers;

		if (cstate->num_mixers)
		_dpu_crtc_setup_lm_bounds(crtc, crtc_state);
		}

		crtc_rect.x2 = mode->hdisplay;
		crtc_rect.y2 = mode->vdisplay;

		/* get plane state for all drm planes associated with crtc state */
		/* FIXME: move this to dpu_plane_atomic_check? */
		drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
		struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate);
		struct drm_rect dst, clip = crtc_rect;

		if (IS_ERR_OR_NULL(pstate)) {
		rc = PTR_ERR(pstate);
		DPU_ERROR("%s: failed to get plane%d state, %d\n",
		dpu_crtc->name, plane->base.id, rc);
		goto end;
		return rc;
		}
		if (cnt >= DPU_STAGE_MAX * 4)
		continue;

		if (!pstate->visible)
		continue;

		pstates[cnt].dpu_pstate = dpu_pstate;
		pstates[cnt].drm_pstate = pstate;
		pstates[cnt].stage = pstate->normalized_zpos;
		pstates[cnt].pipe_id = dpu_plane_pipe(plane);

		dpu_pstate->needs_dirtyfb = needs_dirtyfb;

		if (pipe_staged[pstates[cnt].pipe_id]) {
		multirect_plane[multirect_count].r0 =
		pipe_staged[pstates[cnt].pipe_id];
		multirect_plane[multirect_count].r1 = pstate;
		multirect_count++;

		pipe_staged[pstates[cnt].pipe_id] = NULL;
		} else {
		pipe_staged[pstates[cnt].pipe_id] = pstate;
		}

		cnt++;

		dst = drm_plane_state_dest(pstate);
		if (!drm_rect_intersect(&clip, &dst)) {
		DPU_ERROR("invalid vertical/horizontal destination\n");
		DPU_ERROR("display: " DRM_RECT_FMT " plane: "
		DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect),
		DRM_RECT_ARG(&dst));
		rc = -E2BIG;
		goto end;
		}
		}

		for (i = 1; i < SSPP_MAX; i++) {
		if (pipe_staged[i])
		dpu_plane_clear_multirect(pipe_staged[i]);
		}

		z_pos = -1;
		for (i = 0; i < cnt; i++) {
		/* reset counts at every new blend stage */
		if (pstates[i].stage != z_pos) {
		left_zpos_cnt = 0;
		right_zpos_cnt = 0;
		z_pos = pstates[i].stage;
		}

		/* verify z_pos setting before using it */
		if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) {
		DPU_ERROR("> %d plane stages assigned\n",
		DPU_STAGE_MAX - DPU_STAGE_0);
		rc = -EINVAL;
		goto end;
		} else if (pstates[i].drm_pstate->crtc_x < mixer_width) {
		if (left_zpos_cnt == 2) {
		DPU_ERROR("> 2 planes @ stage %d on left\n",
		z_pos);
		rc = -EINVAL;
		goto end;
		}
		left_zpos_cnt++;

		} else {
		if (right_zpos_cnt == 2) {
		DPU_ERROR("> 2 planes @ stage %d on right\n",
		z_pos);
		rc = -EINVAL;
		goto end;
		}
		right_zpos_cnt++;
		}

		pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0;
		DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos);
		}

		for (i = 0; i < multirect_count; i++) {
		if (dpu_plane_validate_multirect_v2(&multirect_plane[i])) {
		DPU_ERROR(
		"multirect validation failed for planes (%d - %d)\n",
		multirect_plane[i].r0->plane->base.id,
		multirect_plane[i].r1->plane->base.id);
		rc = -EINVAL;
		goto end;
		}
		}

		atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
		@@ -1315,74 +1234,10 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
		if (rc) {
		DPU_ERROR("crtc%d failed performance check %d\n",
		crtc->base.id, rc);
		goto end;
		}

		/* validate source split:
		* use pstates sorted by stage to check planes on same stage
		* we assume that all pipes are in source split so its valid to compare
		* without taking into account left/right mixer placement
		*/
		for (i = 1; i < cnt; i++) {
		struct plane_state prv_pstate, cur_pstate;
		struct drm_rect left_rect, right_rect;
		int32_t left_pid, right_pid;
		int32_t stage;

		prv_pstate = &pstates[i - 1];
		cur_pstate = &pstates[i];
		if (prv_pstate->stage != cur_pstate->stage)
		continue;

		stage = cur_pstate->stage;

		left_pid = prv_pstate->dpu_pstate->base.plane->base.id;
		left_rect = drm_plane_state_dest(prv_pstate->drm_pstate);

		right_pid = cur_pstate->dpu_pstate->base.plane->base.id;
		right_rect = drm_plane_state_dest(cur_pstate->drm_pstate);

		if (right_rect.x1 < left_rect.x1) {
		swap(left_pid, right_pid);
		swap(left_rect, right_rect);
		}

		/**
		* - planes are enumerated in pipe-priority order such that
		* planes with lower drm_id must be left-most in a shared
		* blend-stage when using source split.
		* - planes in source split must be contiguous in width
		* - planes in source split must have same dest yoff and height
		*/
		if (right_pid < left_pid) {
		DPU_ERROR(
		"invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n",
		stage, left_pid, right_pid);
		rc = -EINVAL;
		goto end;
		} else if (right_rect.x1 != drm_rect_width(&left_rect)) {
		DPU_ERROR("non-contiguous coordinates for src split. "
		"stage: %d left: " DRM_RECT_FMT " right: "
		DRM_RECT_FMT "\n", stage,
		DRM_RECT_ARG(&left_rect),
		DRM_RECT_ARG(&right_rect));
		rc = -EINVAL;
		goto end;
		} else if (left_rect.y1 != right_rect.y1 \|\|
		drm_rect_height(&left_rect) != drm_rect_height(&right_rect)) {
		DPU_ERROR("source split at stage: %d. invalid "
		"yoff/height: left: " DRM_RECT_FMT " right: "
		DRM_RECT_FMT "\n", stage,
		DRM_RECT_ARG(&left_rect),
		DRM_RECT_ARG(&right_rect));
		rc = -EINVAL;
		goto end;
		}
		return rc;
		}

		end:
		kfree(pstates);
		return rc;
		return 0;
		}

		int dpu_crtc_vblank(struct drm_crtc *crtc, bool en)
		@@ -1499,8 +1354,16 @@ static int _dpu_debugfs_status_show(struct seq_file s, void data)
		seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
		state->crtc_x, state->crtc_y, state->crtc_w,
		state->crtc_h);
		seq_printf(s, "\tmultirect: mode: %d index: %d\n",
		pstate->multirect_mode, pstate->multirect_index);
		seq_printf(s, "\tsspp[0]:%s\n",
		pstate->pipe.sspp->cap->name);
		seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n",
		pstate->pipe.multirect_mode, pstate->pipe.multirect_index);
		if (pstate->r_pipe.sspp) {
		seq_printf(s, "\tsspp[1]:%s\n",
		pstate->r_pipe.sspp->cap->name);
		seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n",
		pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index);
		}

		seq_puts(s, "\n");
		}

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

+16 −41

Original line number	Diff line number	Diff line
		@@ -545,7 +545,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
		static struct msm_display_topology dpu_encoder_get_topology(
		struct dpu_encoder_virt *dpu_enc,
		struct dpu_kms *dpu_kms,
		struct drm_display_mode *mode)
		struct drm_display_mode *mode,
		struct drm_crtc_state *crtc_state)
		{
		struct msm_display_topology topology = {0};
		int i, intf_count = 0;
		@@ -563,8 +564,7 @@ static struct msm_display_topology dpu_encoder_get_topology(
		* 1 LM, 1 INTF
		* 2 LM, 1 INTF (stream merge to support high resolution interfaces)
		*
		* Adding color blocks only to primary interface if available in
		* sufficient number
		* Add dspps to the reservation requirements if ctm is requested
		*/
		if (intf_count == 2)
		topology.num_lm = 2;
		@@ -573,11 +573,8 @@ static struct msm_display_topology dpu_encoder_get_topology(
		else
		topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;

		if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
		if (dpu_kms->catalog->dspp &&
		(dpu_kms->catalog->dspp_count >= topology.num_lm))
		if (crtc_state->ctm)
		topology.num_dspp = topology.num_lm;
		}

		topology.num_intf = intf_count;

		@@ -638,14 +635,12 @@ static int dpu_encoder_virt_atomic_check(
		if (ret) {
		DPU_ERROR_ENC(dpu_enc,
		"mode unsupported, phys idx %d\n", i);
		break;
		return ret;
		}
		}

		topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
		topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state);

		/* Reserve dynamic resources now. */
		if (!ret) {
		/*
		* Release and Allocate resources on every modeset
		* Dont allocate when active is false.
		@@ -657,7 +652,6 @@ static int dpu_encoder_virt_atomic_check(
		ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
		drm_enc, crtc_state, topology);
		}
		}

		trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags);

		@@ -2094,25 +2088,6 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
		ctl->ops.clear_pending_flush(ctl);
		}

		void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc)
		{
		struct dpu_encoder_virt *dpu_enc;
		struct dpu_encoder_phys *phys;
		int i;

		if (!drm_enc) {
		DPU_ERROR("invalid encoder\n");
		return;
		}
		dpu_enc = to_dpu_encoder_virt(drm_enc);

		for (i = 0; i < dpu_enc->num_phys_encs; i++) {
		phys = dpu_enc->phys_encs[i];
		if (phys->ops.prepare_commit)
		phys->ops.prepare_commit(phys);
		}
		}

		#ifdef CONFIG_DEBUG_FS
		static int _dpu_encoder_status_show(struct seq_file s, void data)
		{

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h

+0 −7

Original line number	Diff line number	Diff line
		@@ -146,13 +146,6 @@ struct drm_encoder *dpu_encoder_init(
		int dpu_encoder_setup(struct drm_device dev, struct drm_encoder enc,
		struct msm_display_info *disp_info);

		/**
		* dpu_encoder_prepare_commit - prepare encoder at the very beginning of an
		* atomic commit, before any registers are written
		* @drm_enc: Pointer to previously created drm encoder structure
		*/
		void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc);

		/**
		* dpu_encoder_set_idle_timeout - set the idle timeout for video
		* and command mode encoders.

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

+5 −3

Original line number	Diff line number	Diff line
		@@ -40,6 +40,8 @@

		#define DPU_ENC_MAX_POLL_TIMEOUT_US 2000

		static void dpu_encoder_phys_cmd_enable_te(struct dpu_encoder_phys *phys_enc);

		static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc)
		{
		return (phys_enc->split_role != ENC_ROLE_SLAVE);
		@@ -565,6 +567,8 @@ static void dpu_encoder_phys_cmd_prepare_for_kickoff(
		phys_enc->hw_pp->idx - PINGPONG_0);
		}

		dpu_encoder_phys_cmd_enable_te(phys_enc);

		DPU_DEBUG_CMDENC(cmd_enc, "pp:%d pending_cnt %d\n",
		phys_enc->hw_pp->idx - PINGPONG_0,
		atomic_read(&phys_enc->pending_kickoff_cnt));
		@@ -586,8 +590,7 @@ static bool dpu_encoder_phys_cmd_is_ongoing_pptx(
		return false;
		}

		static void dpu_encoder_phys_cmd_prepare_commit(
		struct dpu_encoder_phys *phys_enc)
		static void dpu_encoder_phys_cmd_enable_te(struct dpu_encoder_phys *phys_enc)
		{
		struct dpu_encoder_phys_cmd *cmd_enc =
		to_dpu_encoder_phys_cmd(phys_enc);
		@@ -732,7 +735,6 @@ static void dpu_encoder_phys_cmd_trigger_start(
		static void dpu_encoder_phys_cmd_init_ops(
		struct dpu_encoder_phys_ops *ops)
		{
		ops->prepare_commit = dpu_encoder_phys_cmd_prepare_commit;
		ops->is_master = dpu_encoder_phys_cmd_is_master;
		ops->atomic_mode_set = dpu_encoder_phys_cmd_atomic_mode_set;
		ops->enable = dpu_encoder_phys_cmd_enable;