Loading arch/powerpc/oprofile/op_model_cell.c +11 −13 Original line number Original line Diff line number Diff line Loading @@ -658,9 +658,8 @@ static void spu_evnt_swap(unsigned long data) */ */ ret = pm_rtas_activate_signals(cbe_cpu_to_node(cpu), 3); ret = pm_rtas_activate_signals(cbe_cpu_to_node(cpu), 3); if (ret) if (ret) printk(KERN_ERR printk(KERN_ERR "%s: pm_rtas_activate_signals failed, " "%s: pm_rtas_activate_signals failed, SPU event swap\n", "SPU event swap\n", __func__); __func__); /* clear the trace buffer, don't want to take PC for /* clear the trace buffer, don't want to take PC for * previous SPU*/ * previous SPU*/ Loading Loading @@ -1422,8 +1421,7 @@ static int cell_global_start_ppu(struct op_counter_config *ctr) if (ctr_enabled & (1 << i)) { if (ctr_enabled & (1 << i)) { cbe_write_ctr(cpu, i, reset_value[i]); cbe_write_ctr(cpu, i, reset_value[i]); enable_ctr(cpu, i, pm_regs.pm07_cntrl); enable_ctr(cpu, i, pm_regs.pm07_cntrl); interrupt_mask |= interrupt_mask |= CBE_PM_CTR_OVERFLOW_INTR(i); CBE_PM_CTR_OVERFLOW_INTR(i); } else { } else { /* Disable counter */ /* Disable counter */ cbe_write_pm07_control(cpu, i, 0); cbe_write_pm07_control(cpu, i, 0); Loading Loading
arch/powerpc/oprofile/op_model_cell.c +11 −13 Original line number Original line Diff line number Diff line Loading @@ -658,9 +658,8 @@ static void spu_evnt_swap(unsigned long data) */ */ ret = pm_rtas_activate_signals(cbe_cpu_to_node(cpu), 3); ret = pm_rtas_activate_signals(cbe_cpu_to_node(cpu), 3); if (ret) if (ret) printk(KERN_ERR printk(KERN_ERR "%s: pm_rtas_activate_signals failed, " "%s: pm_rtas_activate_signals failed, SPU event swap\n", "SPU event swap\n", __func__); __func__); /* clear the trace buffer, don't want to take PC for /* clear the trace buffer, don't want to take PC for * previous SPU*/ * previous SPU*/ Loading Loading @@ -1422,8 +1421,7 @@ static int cell_global_start_ppu(struct op_counter_config *ctr) if (ctr_enabled & (1 << i)) { if (ctr_enabled & (1 << i)) { cbe_write_ctr(cpu, i, reset_value[i]); cbe_write_ctr(cpu, i, reset_value[i]); enable_ctr(cpu, i, pm_regs.pm07_cntrl); enable_ctr(cpu, i, pm_regs.pm07_cntrl); interrupt_mask |= interrupt_mask |= CBE_PM_CTR_OVERFLOW_INTR(i); CBE_PM_CTR_OVERFLOW_INTR(i); } else { } else { /* Disable counter */ /* Disable counter */ cbe_write_pm07_control(cpu, i, 0); cbe_write_pm07_control(cpu, i, 0); Loading