Commit 25e8b9eb authored by Shawn Guo's avatar Shawn Guo Committed by Ulf Hansson
Browse files

mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check 



As indicated by function esdhc_change_pinstate(), SDR50 and DDR50
require pins_100mhz, while SDR104 and HS400 require pins_200mhz.  Some
system design may support SDR50 and DDR50 with 100mhz pin state only
(without 200mhz one).  Currently the combined 100/200 MHz pinctrl state
check prevents such system from running SDR50 and DDR50.  Separate the
check to support such system design.

Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Reviewed-by: default avatarHaibo Chen <haibo.chen@nxp.com>
Link: https://lore.kernel.org/r/20210326110214.28416-1-shawnguo@kernel.org


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent f0bdf98f

drivers/mmc/host/sdhci-esdhc-imx.c

+4 −4
Original line number Diff line number Diff line
@@ -434,10 +434,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 
			 * Do not advertise faster UHS modes if there are no

			 * pinctrl states for 100MHz/200MHz.

			 */

			if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||

			    IS_ERR_OR_NULL(imx_data->pins_200mhz))

				val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50

					 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);

			if (IS_ERR_OR_NULL(imx_data->pins_100mhz))

				val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);

			if (IS_ERR_OR_NULL(imx_data->pins_200mhz))

				val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);

		}

	}