Commit 25faeddc authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amdgpu: expand cg_flags from u32 to u64 



With this, we can support more CG flags.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 49aa98ca

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+3 −3
Original line number Diff line number Diff line
@@ -179,7 +179,7 @@ extern int amdgpu_sched_jobs; 
extern int amdgpu_sched_hw_submission;

extern uint amdgpu_pcie_gen_cap;

extern uint amdgpu_pcie_lane_cap;

extern uint amdgpu_cg_mask;

extern u64 amdgpu_cg_mask;

extern uint amdgpu_pg_mask;

extern uint amdgpu_sdma_phase_quantum;

extern char *amdgpu_disable_cu;
@@ -322,7 +322,7 @@ int amdgpu_device_ip_set_powergating_state(void *dev, 
					   enum amd_ip_block_type block_type,

					   enum amd_powergating_state state);

void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,

					    u32 *flags);

					    u64 *flags);

int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,

				   enum amd_ip_block_type block_type);

bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
@@ -860,7 +860,7 @@ struct amdgpu_device { 
	/* powerplay */

	struct amd_powerplay		powerplay;

	struct amdgpu_pm		pm;

	u32				cg_flags;

	u64				cg_flags;

	u32				pg_flags;



	/* nbio */

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

+4 −1
Original line number Diff line number Diff line
@@ -758,7 +758,7 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, 
	/* rev==1 */

	config[no_regs++] = adev->rev_id;

	config[no_regs++] = adev->pg_flags;

	config[no_regs++] = adev->cg_flags;

	config[no_regs++] = lower_32_bits(adev->cg_flags);



	/* rev==2 */

	config[no_regs++] = adev->family;
@@ -773,6 +773,9 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, 
	/* rev==4 APU flag */

	config[no_regs++] = adev->flags & AMD_IS_APU ? 1 : 0;



	/* rev==5 CG flag upper 32bit */

	config[no_regs++] = upper_32_bits(adev->cg_flags);



	while (size && (*pos < no_regs * 4)) {

		uint32_t value;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −1
Original line number Diff line number Diff line
@@ -1703,7 +1703,7 @@ int amdgpu_device_ip_set_powergating_state(void *dev, 
 * clockgating is enabled.

 */

void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,

					    u32 *flags)

					    u64 *flags)

{

	int i;

drivers/gpu/drm/amd/amdgpu/amdgpu_df.h

+1 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ struct amdgpu_df_funcs { 
	void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,

						 bool enable);

	void (*get_clockgating_state)(struct amdgpu_device *adev,

				      u32 *flags);

				      u64 *flags);

	void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,

					    bool enable);

	int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+4 −4
Original line number Diff line number Diff line
@@ -136,7 +136,7 @@ int amdgpu_sched_jobs = 32; 
int amdgpu_sched_hw_submission = 2;

uint amdgpu_pcie_gen_cap;

uint amdgpu_pcie_lane_cap;

uint amdgpu_cg_mask = 0xffffffff;

u64 amdgpu_cg_mask = 0xffffffffffffffff;

uint amdgpu_pg_mask = 0xffffffff;

uint amdgpu_sdma_phase_quantum = 32;

char *amdgpu_disable_cu = NULL;
@@ -454,12 +454,12 @@ MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 
module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);



/**

 * DOC: cg_mask (uint)

 * DOC: cg_mask (ullong)

 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in

 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).

 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).

 */

MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");

module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);

module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);



/**

 * DOC: pg_mask (uint)