Commit 26c71d31 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm6350: Add DPU1 nodes 



Add nodes required to enable MDSS/DPU1 on SM6350. There seem to be no
additional changes required to support the derivative SoCs, such as
SM7225.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-7-afcdfb18bb13@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 44bcded2

arch/arm64/boot/dts/qcom/sm6350.dtsi

+218 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com>

 */



#include <dt-bindings/clock/qcom,dispcc-sm6350.h>

#include <dt-bindings/clock/qcom,gcc-sm6350.h>

#include <dt-bindings/clock/qcom,gpucc-sm6350.h>

#include <dt-bindings/clock/qcom,rpmh.h>
@@ -1869,6 +1870,223 @@ camcc: clock-controller@ad00000 { 
			#power-domain-cells = <1>;

		};



		mdss: display-subsystem@ae00000 {

			compatible = "qcom,sm6350-mdss";

			reg = <0 0x0ae00000 0 0x1000>;

			reg-names = "mdss";



			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;

			#interrupt-cells = <1>;



			clocks = <&gcc GCC_DISP_AHB_CLK>,

				 <&gcc GCC_DISP_AXI_CLK>,

				 <&dispcc DISP_CC_MDSS_MDP_CLK>;

			clock-names = "iface",

				      "bus",

				      "core";



			power-domains = <&dispcc MDSS_GDSC>;

			iommus = <&apps_smmu 0x800 0x2>;



			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			status = "disabled";



			mdss_mdp: display-controller@ae01000 {

				compatible = "qcom,sm6350-dpu";

				reg = <0 0x0ae01000 0 0x8f000>,

				      <0 0x0aeb0000 0 0x2008>;

				reg-names = "mdp", "vbif";



				interrupt-parent = <&mdss>;

				interrupts = <0>;



				clocks = <&gcc GCC_DISP_AXI_CLK>,

					 <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&dispcc DISP_CC_MDSS_ROT_CLK>,

					 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,

					 <&dispcc DISP_CC_MDSS_MDP_CLK>,

					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

				clock-names = "bus",

					      "iface",

					      "rot",

					      "lut",

					      "core",

					      "vsync";



				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

				assigned-clock-rates = <19200000>;



				operating-points-v2 = <&mdp_opp_table>;

				power-domains = <&rpmhpd SM6350_CX>;



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						dpu_intf1_out: endpoint {

							remote-endpoint = <&mdss_dsi0_in>;

						};

					};

				};



				mdp_opp_table: opp-table {

					compatible = "operating-points-v2";



					opp-19200000 {

						opp-hz = /bits/ 64 <19200000>;

						required-opps = <&rpmhpd_opp_min_svs>;

					};



					opp-200000000 {

						opp-hz = /bits/ 64 <200000000>;

						required-opps = <&rpmhpd_opp_low_svs>;

					};



					opp-300000000 {

						opp-hz = /bits/ 64 <300000000>;

						required-opps = <&rpmhpd_opp_svs>;

					};



					opp-373333333 {

						opp-hz = /bits/ 64 <373333333>;

						required-opps = <&rpmhpd_opp_svs_l1>;

					};



					opp-448000000 {

						opp-hz = /bits/ 64 <448000000>;

						required-opps = <&rpmhpd_opp_nom>;

					};



					opp-560000000 {

						opp-hz = /bits/ 64 <560000000>;

						required-opps = <&rpmhpd_opp_turbo>;

					};

				};

			};



			mdss_dsi0: dsi@ae94000 {

				compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";

				reg = <0 0x0ae94000 0 0x400>;

				reg-names = "dsi_ctrl";



				interrupt-parent = <&mdss>;

				interrupts = <4>;



				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,

					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,

					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,

					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,

					 <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&gcc GCC_DISP_AXI_CLK>;

				clock-names = "byte",

					      "byte_intf",

					      "pixel",

					      "core",

					      "iface",

					      "bus";



				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,

						  <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;

				assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;



				operating-points-v2 = <&mdss_dsi_opp_table>;

				power-domains = <&rpmhpd SM6350_MX>;



				phys = <&mdss_dsi0_phy>;

				phy-names = "dsi";



				#address-cells = <1>;

				#size-cells = <0>;



				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						mdss_dsi0_in: endpoint {

							remote-endpoint = <&dpu_intf1_out>;

						};

					};



					port@1 {

						reg = <1>;



						mdss_dsi0_out: endpoint {

						};

					};

				};



				mdss_dsi_opp_table: opp-table {

					compatible = "operating-points-v2";



					opp-187500000 {

						opp-hz = /bits/ 64 <187500000>;

						required-opps = <&rpmhpd_opp_low_svs>;

					};



					opp-300000000 {

						opp-hz = /bits/ 64 <300000000>;

						required-opps = <&rpmhpd_opp_svs>;

					};



					opp-358000000 {

						opp-hz = /bits/ 64 <358000000>;

						required-opps = <&rpmhpd_opp_svs_l1>;

					};

				};

			};



			mdss_dsi0_phy: phy@ae94400 {

				compatible = "qcom,dsi-phy-10nm";

				reg = <0 0x0ae94400 0 0x200>,

				      <0 0x0ae94600 0 0x280>,

				      <0 0x0ae94a00 0 0x1e0>;

				reg-names = "dsi_phy",

					    "dsi_phy_lane",

					    "dsi_pll";



				#clock-cells = <1>;

				#phy-cells = <0>;



				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

					 <&rpmhcc RPMH_CXO_CLK>;

				clock-names = "iface", "ref";



				status = "disabled";

			};

		};



		dispcc: clock-controller@af00000 {

			compatible = "qcom,sm6350-dispcc";

			reg = <0 0x0af00000 0 0x20000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_DISP_GPLL0_CLK>,

				 <&mdss_dsi0_phy 0>,

				 <&mdss_dsi0_phy 1>,

				 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,

				 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;

			clock-names = "bi_tcxo",

				      "gcc_disp_gpll0_clk",

				      "dsi0_phy_pll_out_byteclk",

				      "dsi0_phy_pll_out_dsiclk",

				      "dp_phy_pll_link_clk",

				      "dp_phy_pll_vco_div_clk";

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

		};



		pdc: interrupt-controller@b220000 {

			compatible = "qcom,sm6350-pdc", "qcom,pdc";

			reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;