Commit 2723fb7b authored by Atish Patra's avatar Atish Patra Committed by Anup Patel
Browse files

RISC-V: Improve SBI PMU extension related definitions 



This patch fixes/improve few minor things in SBI PMU extension
definition.

1. Align all the firmware event names.
2. Add macros for bit positions in cache event ID & ops.

The changes were small enough to combine them together instead
of creating 1 liner patches.

Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarAtish Patra <atishp@rivosinc.com>
Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 8929283a

arch/riscv/include/asm/sbi.h

+5 −2
Original line number Diff line number Diff line
@@ -169,9 +169,9 @@ enum sbi_pmu_fw_generic_events_t { 
	SBI_PMU_FW_ILLEGAL_INSN		= 4,

	SBI_PMU_FW_SET_TIMER		= 5,

	SBI_PMU_FW_IPI_SENT		= 6,

	SBI_PMU_FW_IPI_RECVD		= 7,

	SBI_PMU_FW_IPI_RCVD		= 7,

	SBI_PMU_FW_FENCE_I_SENT		= 8,

	SBI_PMU_FW_FENCE_I_RECVD	= 9,

	SBI_PMU_FW_FENCE_I_RCVD		= 9,

	SBI_PMU_FW_SFENCE_VMA_SENT	= 10,

	SBI_PMU_FW_SFENCE_VMA_RCVD	= 11,

	SBI_PMU_FW_SFENCE_VMA_ASID_SENT	= 12,
@@ -215,6 +215,9 @@ enum sbi_pmu_ctr_type { 
#define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06

#define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01



#define SBI_PMU_EVENT_CACHE_ID_SHIFT 3

#define SBI_PMU_EVENT_CACHE_OP_SHIFT 1



#define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF



/* Flags defined for config matching function */