Commit 27823278 authored by David Lechner's avatar David Lechner Committed by Sekhar Nori
Browse files

ARM: davinci: switch to common clock framework



This switches ARCH_DAVINCI to use the common clock framework. The legacy
clock code in arch/arm/mach-davinci/ is no longer used. New drivers in
drivers/clk/davinci/ are used instead.

A few macros had to be moved to prevent compilation errors.

Signed-off-by: default avatarDavid Lechner <david@lechnology.com>
Signed-off-by: default avatarSekhar Nori <nsekhar@ti.com>
parent 4d7ee968
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+4 −1
Original line number Diff line number Diff line
@@ -606,13 +606,16 @@ config ARCH_S3C24XX
config ARCH_DAVINCI
	bool "TI DaVinci"
	select ARCH_HAS_HOLES_MEMORYMODEL
	select CLKDEV_LOOKUP
	select COMMON_CLK
	select CPU_ARM926T
	select GENERIC_ALLOCATOR
	select GENERIC_CLOCKEVENTS
	select GENERIC_IRQ_CHIP
	select GPIOLIB
	select HAVE_IDE
	select PM_GENERIC_DOMAINS if PM
	select PM_GENERIC_DOMAINS_OF if PM && OF
	select RESET_CONTROLLER
	select USE_OF
	select ZONE_DMA
	help
+2 −2
Original line number Diff line number Diff line
@@ -5,8 +5,8 @@
#

# Common objects
obj-y 			:= time.o clock.o serial.o psc.o \
			   usb.o common.o sram.o aemif.o
obj-y 					:= time.o serial.o usb.o \
					   common.o sram.o aemif.o

obj-$(CONFIG_DAVINCI_MUX)		+= mux.o

+0 −4
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@@ -12,10 +12,6 @@
#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
#define __ARCH_ARM_DAVINCI_CLOCK_H

#define DAVINCI_PLL1_BASE 0x01c40800
#define DAVINCI_PLL2_BASE 0x01c40c00
#define MAX_PLL 2

/* PLL/Reset register offsets */
#define PLLCTL          0x100
#define PLLCTL_PLLEN    BIT(0)
+4 −0
Original line number Diff line number Diff line
@@ -35,6 +35,10 @@
#include <media/davinci/vpbe.h>
#include <media/davinci/vpbe_osd.h>

#define DAVINCI_PLL1_BASE		0x01c40800
#define DAVINCI_PLL2_BASE		0x01c40c00
#define DAVINCI_PWR_SLEEP_CNTRL_BASE	0x01c41000

#define DAVINCI_SYSTEM_MODULE_BASE	0x01c40000
#define SYSMOD_VDAC_CONFIG		0x2c
#define SYSMOD_VIDCLKCTL		0x38
+0 −2
Original line number Diff line number Diff line
@@ -27,8 +27,6 @@
#ifndef __ASM_ARCH_PSC_H
#define __ASM_ARCH_PSC_H

#define	DAVINCI_PWR_SLEEP_CNTRL_BASE	0x01C41000

/* Power and Sleep Controller (PSC) Domains */
#define DAVINCI_GPSC_ARMDOMAIN		0
#define DAVINCI_GPSC_DSPDOMAIN		1