Commit 283e0a67 authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: fix integer overflow during MSA V_Freq calculation 



[why]
Analyzer shows incorrect V freq in MSA for some large timing.

[how]
Cast an 32 bit integer to uint64_t before multiplication to avoid
integer overflow for a very large timing.

Reviewed-by: default avatarAriel Bernstein <Eric.Bernstein@amd.com>
Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 40169e2f

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c

+2 −2
Original line number Diff line number Diff line
@@ -197,7 +197,7 @@ static void dcn31_hpo_dp_stream_enc_set_stream_attribute( 
	uint32_t h_back_porch;

	uint32_t h_width;

	uint32_t v_height;

	unsigned long long v_freq;

	uint64_t v_freq;

	uint8_t misc0 = 0;

	uint8_t misc1 = 0;

	uint8_t hsp;
@@ -360,7 +360,7 @@ static void dcn31_hpo_dp_stream_enc_set_stream_attribute( 
	v_height = hw_crtc_timing.v_border_top + hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom;

	hsp = hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 0 : 0x80;

	vsp = hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 0 : 0x80;

	v_freq = hw_crtc_timing.pix_clk_100hz * 100;

	v_freq = (uint64_t)hw_crtc_timing.pix_clk_100hz * 100;



	/*   MSA Packet Mapping to 32-bit Link Symbols - DP2 spec, section 2.7.4.1

	 *