Commit 2a411205 authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher
Browse files

drm/amd/display: Add DCN302 support in amdgpu_dm (v2) 



Handle CAVE_DIMGREY_CAVEFISH in amdgpu_dm

v2: fix rebase typo (Alex)

Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 36d26912

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+24 −1
Original line number Diff line number Diff line
@@ -104,6 +104,10 @@ MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); 
#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"

MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

#define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"

MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);

#endif



#define FIRMWARE_RAVEN_DMCU		"amdgpu/raven_dmcu.bin"

MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@@ -1176,6 +1180,9 @@ static int load_dmcu_fw(struct amdgpu_device *adev) 
	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

	case CHIP_DIMGREY_CAVEFISH:

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_01)

	case CHIP_VANGOGH:

#endif
@@ -1291,6 +1298,12 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) 
		fw_name_dmub = FIRMWARE_VANGOGH_DMUB;

		break;

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

	case CHIP_DIMGREY_CAVEFISH:

		dmub_asic = DMUB_ASIC_DCN302;

		fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;

		break;

#endif



	default:

		/* ASIC doesn't support DMUB. */
@@ -3413,6 +3426,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 
	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

	case CHIP_DIMGREY_CAVEFISH:

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_01)

	case CHIP_VANGOGH:

#endif
@@ -3597,6 +3613,9 @@ static int dm_early_init(void *handle) 
		break;

#endif

	case CHIP_NAVI14:

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

	case CHIP_DIMGREY_CAVEFISH:

#endif

		adev->mode_info.num_crtc = 5;

		adev->mode_info.num_hpd = 5;

		adev->mode_info.num_dig = 5;
@@ -3916,6 +3935,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, 
		adev->asic_type == CHIP_SIENNA_CICHLID ||

		adev->asic_type == CHIP_NAVY_FLOUNDER ||

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

		adev->asic_type == CHIP_DIMGREY_CAVEFISH ||

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_01)

		adev->asic_type == CHIP_VANGOGH ||

#endif
@@ -3940,7 +3962,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, 


#ifdef CONFIG_DRM_AMD_DC_DCN3_0

		if (adev->asic_type == CHIP_SIENNA_CICHLID ||

		    adev->asic_type == CHIP_NAVY_FLOUNDER)

		    adev->asic_type == CHIP_NAVY_FLOUNDER ||

		    adev->asic_type == CHIP_DIMGREY_CAVEFISH)

			tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;

#endif

		ret = fill_plane_dcc_attributes(adev, afb, format, rotation,