Loading include/sound/soc.h +1 −0 Original line number Diff line number Diff line Loading @@ -1141,6 +1141,7 @@ struct snd_soc_pcm_runtime { unsigned int num_codecs; struct delayed_work delayed_work; void (*close_delayed_work_func)(struct snd_soc_pcm_runtime *rtd); #ifdef CONFIG_DEBUG_FS struct dentry *debugfs_dpcm_root; #endif Loading sound/soc/amd/acp-da7219-max98357a.c +14 −32 Original line number Diff line number Diff line Loading @@ -96,14 +96,19 @@ static int cz_da7219_init(struct snd_soc_pcm_runtime *rtd) return 0; } static int da7219_clk_enable(struct snd_pcm_substream *substream, int wclk_rate, int bclk_rate) static int da7219_clk_enable(struct snd_pcm_substream *substream) { int ret = 0; struct snd_soc_pcm_runtime *rtd = substream->private_data; clk_set_rate(da7219_dai_wclk, wclk_rate); clk_set_rate(da7219_dai_bclk, bclk_rate); /* * Set wclk to 48000 because the rate constraint of this driver is * 48000. ADAU7002 spec: "The ADAU7002 requires a BCLK rate that is * minimum of 64x the LRCLK sample rate." DA7219 is the only clk * source so for all codecs we have to limit bclk to 64X lrclk. */ clk_set_rate(da7219_dai_wclk, 48000); clk_set_rate(da7219_dai_bclk, 48000 * 64); ret = clk_prepare_enable(da7219_dai_bclk); if (ret < 0) { dev_err(rtd->dev, "can't enable master clock %d\n", ret); Loading Loading @@ -156,7 +161,7 @@ static int cz_da7219_play_startup(struct snd_pcm_substream *substream) &constraints_rates); machine->play_i2s_instance = I2S_SP_INSTANCE; return 0; return da7219_clk_enable(substream); } static int cz_da7219_cap_startup(struct snd_pcm_substream *substream) Loading @@ -178,7 +183,7 @@ static int cz_da7219_cap_startup(struct snd_pcm_substream *substream) machine->cap_i2s_instance = I2S_SP_INSTANCE; machine->capture_channel = CAP_CHANNEL1; return 0; return da7219_clk_enable(substream); } static int cz_max_startup(struct snd_pcm_substream *substream) Loading @@ -199,7 +204,7 @@ static int cz_max_startup(struct snd_pcm_substream *substream) &constraints_rates); machine->play_i2s_instance = I2S_BT_INSTANCE; return 0; return da7219_clk_enable(substream); } static int cz_dmic0_startup(struct snd_pcm_substream *substream) Loading @@ -220,7 +225,7 @@ static int cz_dmic0_startup(struct snd_pcm_substream *substream) &constraints_rates); machine->cap_i2s_instance = I2S_BT_INSTANCE; return 0; return da7219_clk_enable(substream); } static int cz_dmic1_startup(struct snd_pcm_substream *substream) Loading @@ -242,25 +247,7 @@ static int cz_dmic1_startup(struct snd_pcm_substream *substream) machine->cap_i2s_instance = I2S_SP_INSTANCE; machine->capture_channel = CAP_CHANNEL0; return 0; } static int cz_da7219_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { int wclk, bclk; wclk = params_rate(params); bclk = wclk * params_channels(params) * snd_pcm_format_width(params_format(params)); /* ADAU7002 spec: "The ADAU7002 requires a BCLK rate * that is minimum of 64x the LRCLK sample rate." * DA7219 is the only clk source so for all codecs * we have to limit bclk to 64X lrclk. */ if (bclk < (wclk * 64)) bclk = wclk * 64; return da7219_clk_enable(substream, wclk, bclk); return da7219_clk_enable(substream); } static void cz_da7219_shutdown(struct snd_pcm_substream *substream) Loading @@ -271,31 +258,26 @@ static void cz_da7219_shutdown(struct snd_pcm_substream *substream) static const struct snd_soc_ops cz_da7219_play_ops = { .startup = cz_da7219_play_startup, .shutdown = cz_da7219_shutdown, .hw_params = cz_da7219_params, }; static const struct snd_soc_ops cz_da7219_cap_ops = { .startup = cz_da7219_cap_startup, .shutdown = cz_da7219_shutdown, .hw_params = cz_da7219_params, }; static const struct snd_soc_ops cz_max_play_ops = { .startup = cz_max_startup, .shutdown = cz_da7219_shutdown, .hw_params = cz_da7219_params, }; static const struct snd_soc_ops cz_dmic0_cap_ops = { .startup = cz_dmic0_startup, .shutdown = cz_da7219_shutdown, .hw_params = cz_da7219_params, }; static const struct snd_soc_ops cz_dmic1_cap_ops = { .startup = cz_dmic1_startup, .shutdown = cz_da7219_shutdown, .hw_params = cz_da7219_params, }; SND_SOC_DAILINK_DEF(designware1, Loading sound/soc/codecs/max98090.c +21 −9 Original line number Diff line number Diff line Loading @@ -2294,28 +2294,42 @@ static void max98090_pll_det_disable_work(struct work_struct *work) M98090_IULK_MASK, 0); } static void max98090_pll_work(struct work_struct *work) static void max98090_pll_work(struct max98090_priv *max98090) { struct max98090_priv *max98090 = container_of(work, struct max98090_priv, pll_work); struct snd_soc_component *component = max98090->component; unsigned int pll; int i; if (!snd_soc_component_is_active(component)) return; dev_info_ratelimited(component->dev, "PLL unlocked\n"); /* * As the datasheet suggested, the maximum PLL lock time should be * 7 msec. The workaround resets the codec softly by toggling SHDN * off and on if PLL failed to lock for 10 msec. Notably, there is * no suggested hold time for SHDN off. */ /* Toggle shutdown OFF then ON */ mutex_lock(&component->card->dapm_mutex); snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, M98090_SHDNN_MASK, 0); msleep(10); snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, M98090_SHDNN_MASK, M98090_SHDNN_MASK); mutex_unlock(&component->card->dapm_mutex); for (i = 0; i < 10; ++i) { /* Give PLL time to lock */ msleep(10); usleep_range(1000, 1200); /* Check lock status */ pll = snd_soc_component_read32( component, M98090_REG_DEVICE_STATUS); if (!(pll & M98090_ULK_MASK)) break; } } static void max98090_jack_work(struct work_struct *work) Loading Loading @@ -2452,7 +2466,7 @@ static irqreturn_t max98090_interrupt(int irq, void *data) if (active & M98090_ULK_MASK) { dev_dbg(component->dev, "M98090_ULK_MASK\n"); schedule_work(&max98090->pll_work); max98090_pll_work(max98090); } if (active & M98090_JDET_MASK) { Loading Loading @@ -2615,7 +2629,6 @@ static int max98090_probe(struct snd_soc_component *component) max98090_pll_det_enable_work); INIT_WORK(&max98090->pll_det_disable_work, max98090_pll_det_disable_work); INIT_WORK(&max98090->pll_work, max98090_pll_work); /* Enable jack detection */ snd_soc_component_write(component, M98090_REG_JACK_DETECT, Loading Loading @@ -2678,7 +2691,6 @@ static void max98090_remove(struct snd_soc_component *component) cancel_delayed_work_sync(&max98090->jack_work); cancel_delayed_work_sync(&max98090->pll_det_enable_work); cancel_work_sync(&max98090->pll_det_disable_work); cancel_work_sync(&max98090->pll_work); max98090->component = NULL; } Loading sound/soc/codecs/max98090.h +0 −1 Original line number Diff line number Diff line Loading @@ -1530,7 +1530,6 @@ struct max98090_priv { struct delayed_work jack_work; struct delayed_work pll_det_enable_work; struct work_struct pll_det_disable_work; struct work_struct pll_work; struct snd_soc_jack *jack; unsigned int dai_fmt; int tdm_slots; Loading sound/soc/codecs/rt5677-spi.h +16 −0 Original line number Diff line number Diff line Loading @@ -9,9 +9,25 @@ #ifndef __RT5677_SPI_H__ #define __RT5677_SPI_H__ #if IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI) int rt5677_spi_read(u32 addr, void *rxbuf, size_t len); int rt5677_spi_write(u32 addr, const void *txbuf, size_t len); int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw); void rt5677_spi_hotword_detected(void); #else static inline int rt5677_spi_read(u32 addr, void *rxbuf, size_t len) { return -EINVAL; } static inline int rt5677_spi_write(u32 addr, const void *txbuf, size_t len) { return -EINVAL; } static inline int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw) { return -EINVAL; } static inline void rt5677_spi_hotword_detected(void){} #endif #endif /* __RT5677_SPI_H__ */ Loading
include/sound/soc.h +1 −0 Original line number Diff line number Diff line Loading @@ -1141,6 +1141,7 @@ struct snd_soc_pcm_runtime { unsigned int num_codecs; struct delayed_work delayed_work; void (*close_delayed_work_func)(struct snd_soc_pcm_runtime *rtd); #ifdef CONFIG_DEBUG_FS struct dentry *debugfs_dpcm_root; #endif Loading
sound/soc/amd/acp-da7219-max98357a.c +14 −32 Original line number Diff line number Diff line Loading @@ -96,14 +96,19 @@ static int cz_da7219_init(struct snd_soc_pcm_runtime *rtd) return 0; } static int da7219_clk_enable(struct snd_pcm_substream *substream, int wclk_rate, int bclk_rate) static int da7219_clk_enable(struct snd_pcm_substream *substream) { int ret = 0; struct snd_soc_pcm_runtime *rtd = substream->private_data; clk_set_rate(da7219_dai_wclk, wclk_rate); clk_set_rate(da7219_dai_bclk, bclk_rate); /* * Set wclk to 48000 because the rate constraint of this driver is * 48000. ADAU7002 spec: "The ADAU7002 requires a BCLK rate that is * minimum of 64x the LRCLK sample rate." DA7219 is the only clk * source so for all codecs we have to limit bclk to 64X lrclk. */ clk_set_rate(da7219_dai_wclk, 48000); clk_set_rate(da7219_dai_bclk, 48000 * 64); ret = clk_prepare_enable(da7219_dai_bclk); if (ret < 0) { dev_err(rtd->dev, "can't enable master clock %d\n", ret); Loading Loading @@ -156,7 +161,7 @@ static int cz_da7219_play_startup(struct snd_pcm_substream *substream) &constraints_rates); machine->play_i2s_instance = I2S_SP_INSTANCE; return 0; return da7219_clk_enable(substream); } static int cz_da7219_cap_startup(struct snd_pcm_substream *substream) Loading @@ -178,7 +183,7 @@ static int cz_da7219_cap_startup(struct snd_pcm_substream *substream) machine->cap_i2s_instance = I2S_SP_INSTANCE; machine->capture_channel = CAP_CHANNEL1; return 0; return da7219_clk_enable(substream); } static int cz_max_startup(struct snd_pcm_substream *substream) Loading @@ -199,7 +204,7 @@ static int cz_max_startup(struct snd_pcm_substream *substream) &constraints_rates); machine->play_i2s_instance = I2S_BT_INSTANCE; return 0; return da7219_clk_enable(substream); } static int cz_dmic0_startup(struct snd_pcm_substream *substream) Loading @@ -220,7 +225,7 @@ static int cz_dmic0_startup(struct snd_pcm_substream *substream) &constraints_rates); machine->cap_i2s_instance = I2S_BT_INSTANCE; return 0; return da7219_clk_enable(substream); } static int cz_dmic1_startup(struct snd_pcm_substream *substream) Loading @@ -242,25 +247,7 @@ static int cz_dmic1_startup(struct snd_pcm_substream *substream) machine->cap_i2s_instance = I2S_SP_INSTANCE; machine->capture_channel = CAP_CHANNEL0; return 0; } static int cz_da7219_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { int wclk, bclk; wclk = params_rate(params); bclk = wclk * params_channels(params) * snd_pcm_format_width(params_format(params)); /* ADAU7002 spec: "The ADAU7002 requires a BCLK rate * that is minimum of 64x the LRCLK sample rate." * DA7219 is the only clk source so for all codecs * we have to limit bclk to 64X lrclk. */ if (bclk < (wclk * 64)) bclk = wclk * 64; return da7219_clk_enable(substream, wclk, bclk); return da7219_clk_enable(substream); } static void cz_da7219_shutdown(struct snd_pcm_substream *substream) Loading @@ -271,31 +258,26 @@ static void cz_da7219_shutdown(struct snd_pcm_substream *substream) static const struct snd_soc_ops cz_da7219_play_ops = { .startup = cz_da7219_play_startup, .shutdown = cz_da7219_shutdown, .hw_params = cz_da7219_params, }; static const struct snd_soc_ops cz_da7219_cap_ops = { .startup = cz_da7219_cap_startup, .shutdown = cz_da7219_shutdown, .hw_params = cz_da7219_params, }; static const struct snd_soc_ops cz_max_play_ops = { .startup = cz_max_startup, .shutdown = cz_da7219_shutdown, .hw_params = cz_da7219_params, }; static const struct snd_soc_ops cz_dmic0_cap_ops = { .startup = cz_dmic0_startup, .shutdown = cz_da7219_shutdown, .hw_params = cz_da7219_params, }; static const struct snd_soc_ops cz_dmic1_cap_ops = { .startup = cz_dmic1_startup, .shutdown = cz_da7219_shutdown, .hw_params = cz_da7219_params, }; SND_SOC_DAILINK_DEF(designware1, Loading
sound/soc/codecs/max98090.c +21 −9 Original line number Diff line number Diff line Loading @@ -2294,28 +2294,42 @@ static void max98090_pll_det_disable_work(struct work_struct *work) M98090_IULK_MASK, 0); } static void max98090_pll_work(struct work_struct *work) static void max98090_pll_work(struct max98090_priv *max98090) { struct max98090_priv *max98090 = container_of(work, struct max98090_priv, pll_work); struct snd_soc_component *component = max98090->component; unsigned int pll; int i; if (!snd_soc_component_is_active(component)) return; dev_info_ratelimited(component->dev, "PLL unlocked\n"); /* * As the datasheet suggested, the maximum PLL lock time should be * 7 msec. The workaround resets the codec softly by toggling SHDN * off and on if PLL failed to lock for 10 msec. Notably, there is * no suggested hold time for SHDN off. */ /* Toggle shutdown OFF then ON */ mutex_lock(&component->card->dapm_mutex); snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, M98090_SHDNN_MASK, 0); msleep(10); snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, M98090_SHDNN_MASK, M98090_SHDNN_MASK); mutex_unlock(&component->card->dapm_mutex); for (i = 0; i < 10; ++i) { /* Give PLL time to lock */ msleep(10); usleep_range(1000, 1200); /* Check lock status */ pll = snd_soc_component_read32( component, M98090_REG_DEVICE_STATUS); if (!(pll & M98090_ULK_MASK)) break; } } static void max98090_jack_work(struct work_struct *work) Loading Loading @@ -2452,7 +2466,7 @@ static irqreturn_t max98090_interrupt(int irq, void *data) if (active & M98090_ULK_MASK) { dev_dbg(component->dev, "M98090_ULK_MASK\n"); schedule_work(&max98090->pll_work); max98090_pll_work(max98090); } if (active & M98090_JDET_MASK) { Loading Loading @@ -2615,7 +2629,6 @@ static int max98090_probe(struct snd_soc_component *component) max98090_pll_det_enable_work); INIT_WORK(&max98090->pll_det_disable_work, max98090_pll_det_disable_work); INIT_WORK(&max98090->pll_work, max98090_pll_work); /* Enable jack detection */ snd_soc_component_write(component, M98090_REG_JACK_DETECT, Loading Loading @@ -2678,7 +2691,6 @@ static void max98090_remove(struct snd_soc_component *component) cancel_delayed_work_sync(&max98090->jack_work); cancel_delayed_work_sync(&max98090->pll_det_enable_work); cancel_work_sync(&max98090->pll_det_disable_work); cancel_work_sync(&max98090->pll_work); max98090->component = NULL; } Loading
sound/soc/codecs/max98090.h +0 −1 Original line number Diff line number Diff line Loading @@ -1530,7 +1530,6 @@ struct max98090_priv { struct delayed_work jack_work; struct delayed_work pll_det_enable_work; struct work_struct pll_det_disable_work; struct work_struct pll_work; struct snd_soc_jack *jack; unsigned int dai_fmt; int tdm_slots; Loading
sound/soc/codecs/rt5677-spi.h +16 −0 Original line number Diff line number Diff line Loading @@ -9,9 +9,25 @@ #ifndef __RT5677_SPI_H__ #define __RT5677_SPI_H__ #if IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI) int rt5677_spi_read(u32 addr, void *rxbuf, size_t len); int rt5677_spi_write(u32 addr, const void *txbuf, size_t len); int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw); void rt5677_spi_hotword_detected(void); #else static inline int rt5677_spi_read(u32 addr, void *rxbuf, size_t len) { return -EINVAL; } static inline int rt5677_spi_write(u32 addr, const void *txbuf, size_t len) { return -EINVAL; } static inline int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw) { return -EINVAL; } static inline void rt5677_spi_hotword_detected(void){} #endif #endif /* __RT5677_SPI_H__ */