Commit 2c2dd055 authored by Haohui Mai's avatar Haohui Mai Committed by Alex Deucher
Browse files

drm/amdgpu: Clean up of initializing doorbells for gfx_v9 and gfx_v10 



Clean up redundant, copy-paste code blocks during the initialization of
the doorbells in mqd_init().

Signed-off-by: default avatarHaohui Mai <ricetons@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c51bdd1a

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+0 −17
Original line number Diff line number Diff line
@@ -6919,23 +6919,6 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 
	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;

	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;



	tmp = 0;

	/* enable the doorbell if requested */

	if (prop->use_doorbell) {

		tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);

		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

				DOORBELL_OFFSET, prop->doorbell_index);



		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

				    DOORBELL_EN, 1);

		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

				    DOORBELL_SOURCE, 0);

		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

				    DOORBELL_HIT, 0);

	}



	mqd->cp_hqd_pq_doorbell_control = tmp;



	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */

	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+0 −17
Original line number Diff line number Diff line
@@ -3535,23 +3535,6 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 
	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;

	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;



	tmp = 0;

	/* enable the doorbell if requested */

	if (ring->use_doorbell) {

		tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);

		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

				DOORBELL_OFFSET, ring->doorbell_index);



		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

					 DOORBELL_EN, 1);

		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

					 DOORBELL_SOURCE, 0);

		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

					 DOORBELL_HIT, 0);

	}



	mqd->cp_hqd_pq_doorbell_control = tmp;



	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */

	ring->wptr = 0;

	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);