usb: dwc3: add definitions for new registers

#define DWC3_DEVICE_EVENT_CONNECT_DONE		2

#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE	3

#define DWC3_DEVICE_EVENT_WAKEUP		4

#define DWC3_DEVICE_EVENT_HIBER_REQ		5

#define DWC3_DEVICE_EVENT_EOPF			6

#define DWC3_DEVICE_EVENT_SOF			7

#define DWC3_DEVICE_EVENT_ERRATIC_ERROR		9

#define DWC3_GCTL_SCALEDOWN(n)		((n) << 4)

#define DWC3_GCTL_SCALEDOWN_MASK	DWC3_GCTL_SCALEDOWN(3)

#define DWC3_GCTL_DISSCRAMBLE		(1 << 3)

#define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)

#define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)

/* Global USB2 PHY Configuration Register */

#define DWC3_GHWPARAMS1_EN_PWROPT(n)	(((n) & (3 << 24)) >> 24)

#define DWC3_GHWPARAMS1_EN_PWROPT_NO	0

#define DWC3_GHWPARAMS1_EN_PWROPT_CLK	1

#define DWC3_GHWPARAMS1_EN_PWROPT_HIB	2

#define DWC3_GHWPARAMS1_PWROPT(n)	((n) << 24)

#define DWC3_GHWPARAMS1_PWROPT_MASK	DWC3_GHWPARAMS1_PWROPT(3)

/* Global HWPARAMS4 Register */

#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n)	(((n) & (0x0f << 13)) >> 13)

#define DWC3_MAX_HIBER_SCRATCHBUFS		15

/* Device Configuration Register */

#define DWC3_DCFG_LPM_CAP	(1 << 22)

#define DWC3_DCFG_LOWSPEED	(2 << 0)

#define DWC3_DCFG_FULLSPEED1	(3 << 0)

#define DWC3_DCFG_LPM_CAP	(1 << 22)

/* Device Control Register */

#define DWC3_DCTL_RUN_STOP	(1 << 31)

#define DWC3_DCTL_CSFTRST	(1 << 30)

#define DWC3_DCTL_APPL1RES	(1 << 23)

/* These apply for core versions 1.87a and earlier */

#define DWC3_DCTL_TRGTULST_MASK		(0x0f << 17)

#define DWC3_DCTL_TRGTULST(n)		((n) << 17)

#define DWC3_DCTL_TRGTULST_U2		(DWC3_DCTL_TRGTULST(2))

#define DWC3_DCTL_TRGTULST_U3		(DWC3_DCTL_TRGTULST(3))

#define DWC3_DCTL_TRGTULST_SS_DIS	(DWC3_DCTL_TRGTULST(4))

#define DWC3_DCTL_TRGTULST_RX_DET	(DWC3_DCTL_TRGTULST(5))

#define DWC3_DCTL_TRGTULST_SS_INACT	(DWC3_DCTL_TRGTULST(6))

/* These apply for core versions 1.94a and later */

#define DWC3_DCTL_KEEP_CONNECT	(1 << 19)

#define DWC3_DCTL_L1_HIBER_EN	(1 << 18)

#define DWC3_DCTL_CRS		(1 << 17)

#define DWC3_DCTL_CSS		(1 << 16)

#define DWC3_DCTL_INITU2ENA	(1 << 12)

#define DWC3_DCTL_ACCEPTU2ENA	(1 << 11)

#define DWC3_DCTL_INITU1ENA	(1 << 10)

#define DWC3_DEVTEN_ERRTICERREN		(1 << 9)

#define DWC3_DEVTEN_SOFEN		(1 << 7)

#define DWC3_DEVTEN_EOPFEN		(1 << 6)

#define DWC3_DEVTEN_HIBERNATIONREQEVTEN	(1 << 5)

#define DWC3_DEVTEN_WKUPEVTEN		(1 << 4)

#define DWC3_DEVTEN_ULSTCNGEN		(1 << 3)

#define DWC3_DEVTEN_CONNECTDONEEN	(1 << 2)

#define DWC3_DEVTEN_DISCONNEVTEN	(1 << 0)

/* Device Status Register */

#define DWC3_DSTS_DCNRD			(1 << 29)

/* This applies for core versions 1.87a and earlier */

#define DWC3_DSTS_PWRUPREQ		(1 << 24)

/* These apply for core versions 1.94a and later */

#define DWC3_DSTS_RSS			(1 << 25)

#define DWC3_DSTS_SSS			(1 << 24)

#define DWC3_DSTS_COREIDLE		(1 << 23)

#define DWC3_DSTS_DEVCTRLHLT		(1 << 22)

#define DWC3_DGCMD_SET_LMP		0x01

#define DWC3_DGCMD_SET_PERIODIC_PAR	0x02

#define DWC3_DGCMD_XMIT_FUNCTION	0x03

/* These apply for core versions 1.94a and later */

#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO	0x04

#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI	0x05

#define DWC3_DGCMD_SELECTED_FIFO_FLUSH	0x09

#define DWC3_DGCMD_ALL_FIFO_FLUSH	0x0a

#define DWC3_DGCMD_SET_ENDPOINT_NRDY	0x0c

#define DWC3_DGCMD_STATUS(n)		(((n) >> 15) & 1)

#define DWC3_DGCMD_CMDACT		(1 << 10)

#define DWC3_DGCMD_CMDIOC		(1 << 8)

/* Device Generic Command Parameter Register */

#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT	(1 << 0)

#define DWC3_DGCMDPAR_FIFO_NUM(n)		((n) << 0)

#define DWC3_DGCMDPAR_RX_FIFO			(0 << 5)

#define DWC3_DGCMDPAR_TX_FIFO			(1 << 5)

#define DWC3_DGCMDPAR_LOOPBACK_DIS		(0 << 0)

#define DWC3_DGCMDPAR_LOOPBACK_ENA		(1 << 0)

/* Device Endpoint Command Register */

#define DWC3_DEPCMD_PARAM_SHIFT		16

#define DWC3_DEPCMD_STARTTRANSFER	(0x06 << 0)

#define DWC3_DEPCMD_CLEARSTALL		(0x05 << 0)

#define DWC3_DEPCMD_SETSTALL		(0x04 << 0)

/* This applies for core versions 1.90a and earlier */

#define DWC3_DEPCMD_GETSEQNUMBER	(0x03 << 0)

/* This applies for core versions 1.94a and later */

#define DWC3_DEPCMD_GETEPSTATE		(0x03 << 0)

#define DWC3_DEPCMD_SETTRANSFRESOURCE	(0x02 << 0)

#define DWC3_DEPCMD_SETEPCONFIG		(0x01 << 0)

	DWC3_LINK_STATE_HRESET		= 0x09,

	DWC3_LINK_STATE_CMPLY		= 0x0a,

	DWC3_LINK_STATE_LPBK		= 0x0b,

	DWC3_LINK_STATE_RESET		= 0x0e,

	DWC3_LINK_STATE_RESUME		= 0x0f,

	DWC3_LINK_STATE_MASK		= 0x0f,

};

#define DWC3_TRBSTS_OK			0

#define DWC3_TRBSTS_MISSED_ISOC		1

#define DWC3_TRBSTS_SETUP_PENDING	2

#define DWC3_TRB_STS_XFER_IN_PROG	4

/* TRB Control */

#define DWC3_TRB_CTRL_HWO		(1 << 0)

	unsigned		queued:1;

};

/*

 * struct dwc3_scratchpad_array - hibernation scratchpad array

 * (format defined by hw)

 */

struct dwc3_scratchpad_array {

	__le64	dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];

};

/**

 * struct dwc3 - representation of our controller

 * @ctrl_req: usb control request which is used for ep0

#define DWC3_REVISION_180A	0x5533180a

#define DWC3_REVISION_183A	0x5533183a

#define DWC3_REVISION_185A	0x5533185a

#define DWC3_REVISION_187A	0x5533187a

#define DWC3_REVISION_188A	0x5533188a

#define DWC3_REVISION_190A	0x5533190a

#define DWC3_REVISION_194A	0x5533194a

#define DWC3_REVISION_200A	0x5533200a

#define DWC3_REVISION_202A	0x5533202a

#define DWC3_REVISION_210A	0x5533210a

#define DWC3_DEPCFG_FIFO_NUMBER(n)	((n) << 17)

#define DWC3_DEPCFG_BURST_SIZE(n)	((n) << 22)

#define DWC3_DEPCFG_DATA_SEQ_NUM(n)	((n) << 26)

/* This applies for core versions earlier than 1.94a */

#define DWC3_DEPCFG_IGN_SEQ_NUM		(1 << 31)

/* These apply for core versions 1.94a and later */

#define DWC3_DEPCFG_ACTION_INIT		(0 << 30)

#define DWC3_DEPCFG_ACTION_RESTORE	(1 << 30)

#define DWC3_DEPCFG_ACTION_MODIFY	(2 << 30)

/* DEPXFERCFG parameter 0 */

#define DWC3_DEPXFERCFG_NUM_XFER_RES(n)	((n) & 0xffff)