Commit 2ca6c483 authored by Wesley Chalmers's avatar Wesley Chalmers Committed by Alex Deucher
Browse files

drm/amd/display: Add reg defs for DCN303 



[WHY]
These registers are currently missing from the DCN303 header files

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarGeorge Shen <George.Shen@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarWesley Chalmers <Wesley.Chalmers@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 458c79a8

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h

+18 −2
Original line number Diff line number Diff line
@@ -15,7 +15,11 @@ 
	SR(DPPCLK_DTO_CTRL),\

	DCCG_SRII(DTO_PARAM, DPPCLK, 0),\

	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\

	SR(REFCLK_CNTL)

	SR(REFCLK_CNTL),\

	SR(DISPCLK_FREQ_CHANGE_CNTL),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\

	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1)





#define DCCG_MASK_SH_LIST_DCN3_03(mask_sh) \

		DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
@@ -25,6 +29,18 @@ 
		DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\

		DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\

		DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\

		DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)

		DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\

		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\

		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\

		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\

		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\

		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\

		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\

		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\

		DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\

		DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\

		DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\

		DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\

		DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)



#endif //__DCN303_DCCG_H__