Commit 2d90a1c0 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
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drm/amd/display: Defer DIG FIFO disable after VID stream enable 



[Why]
On some monitors we see a brief flash of corruption during the
monitor disable sequence caused by FIFO being disabled in the middle
of an active DP stream.

[How]
Wait until DP vid stream is disabled before turning off the FIFO.

The FIFO reset on DP unblank should take care of clearing any FIFO
error, if any.

Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: default avatarSyed Hassan <Syed.Hassan@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a1cbe691

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c

+3 −3
Original line number Diff line number Diff line
@@ -278,10 +278,10 @@ static void enc314_stream_encoder_dp_blank( 
	struct dc_link *link,

	struct stream_encoder *enc)

{

	/* New to DCN314 - disable the FIFO before VID stream disable. */

	enc314_disable_fifo(enc);



	enc1_stream_encoder_dp_blank(link, enc);



	/* Disable FIFO after the DP vid stream is disabled to avoid corruption. */

	enc314_disable_fifo(enc);

}



static void enc314_stream_encoder_dp_unblank(