Skip to content
Commit 2dcb305a authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Ulf Hansson
Browse files

mmc: sunxi: Support MMC_DDR52 timing modes



DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52).
Consider MMC_DDR52 when setting clock delays.

Since MMC high speed mode goes up to 52 MHz instead of 50 MHz for SD,
and this number is visible in the capability macro, increase the
clock rate upper limit to 52 MHz.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Reviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent ed9feec7
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment