Commit 2e8c07c3 authored by Divy Le Ray's avatar Divy Le Ray Committed by David S. Miller
Browse files

cxgb3: use request_firmware() for the EDC registers setup 



use request_firmware() to load the phy's EDC programmation

Signed-off-by: default avatarDivy Le Ray <divy@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 5e659515

drivers/net/cxgb3/adapter.h

+2 −0
Original line number Diff line number Diff line
@@ -320,4 +320,6 @@ int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx, 
		unsigned char *data);

irqreturn_t t3_sge_intr_msix(int irq, void *cookie);



int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size);



#endif				/* __T3_ADAPTER_H__ */

drivers/net/cxgb3/ael1002.c

+31 −1050

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/cxgb3/common.h

+10 −0
Original line number Diff line number Diff line
@@ -566,6 +566,15 @@ struct cphy_ops { 


	u32 mmds;

};

enum {

	EDC_OPT_AEL2005 = 0,

	EDC_OPT_AEL2005_SIZE = 1084,

	EDC_TWX_AEL2005 = 1,

	EDC_TWX_AEL2005_SIZE = 1464,

	EDC_TWX_AEL2020 = 2,

	EDC_TWX_AEL2020_SIZE = 1628,

	EDC_MAX_SIZE = EDC_TWX_AEL2020_SIZE, /* Max cache size */

};



/* A PHY instance */

struct cphy {
@@ -577,6 +586,7 @@ struct cphy { 
	unsigned long fifo_errors;	/* FIFO over/under-flows */

	const struct cphy_ops *ops;	/* PHY operations */

	struct mdio_if_info mdio;

	u16 phy_cache[EDC_MAX_SIZE];	/* EDC cache */

};



/* Convenience MDIO read/write wrappers */

drivers/net/cxgb3/cxgb3_main.c

+69 −0
Original line number Diff line number Diff line
@@ -964,6 +964,75 @@ static int bind_qsets(struct adapter *adap) 


#define FW_FNAME "cxgb3/t3fw-%d.%d.%d.bin"

#define TPSRAM_NAME "cxgb3/t3%c_psram-%d.%d.%d.bin"

#define AEL2005_OPT_EDC_NAME "cxgb3/ael2005_opt_edc.bin"

#define AEL2005_TWX_EDC_NAME "cxgb3/ael2005_twx_edc.bin"

#define AEL2020_TWX_EDC_NAME "cxgb3/ael2005_twx_edc.bin"



static inline const char *get_edc_fw_name(int edc_idx)

{

	const char *fw_name = NULL;



	switch (edc_idx) {

	case EDC_OPT_AEL2005:

		fw_name = AEL2005_OPT_EDC_NAME;

		break;

	case EDC_TWX_AEL2005:

		fw_name = AEL2005_TWX_EDC_NAME;

		break;

	case EDC_TWX_AEL2020:

		fw_name = AEL2020_TWX_EDC_NAME;

		break;

	}

	return fw_name;

}



int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size)

{

	struct adapter *adapter = phy->adapter;

	const struct firmware *fw;

	char buf[64];

	u32 csum;

	const __be32 *p;

	u16 *cache = phy->phy_cache;

	int i, ret;



	snprintf(buf, sizeof(buf), get_edc_fw_name(edc_idx));



	ret = request_firmware(&fw, buf, &adapter->pdev->dev);

	if (ret < 0) {

		dev_err(&adapter->pdev->dev,

			"could not upgrade firmware: unable to load %s\n",

			buf);

		return ret;

	}



	/* check size, take checksum in account */

	if (fw->size > size + 4) {

		CH_ERR(adapter, "firmware image too large %u, expected %d\n",

		       (unsigned int)fw->size, size + 4);

		ret = -EINVAL;

	}



	/* compute checksum */

	p = (const __be32 *)fw->data;

	for (csum = 0, i = 0; i < fw->size / sizeof(csum); i++)

		csum += ntohl(p[i]);



	if (csum != 0xffffffff) {

		CH_ERR(adapter, "corrupted firmware image, checksum %u\n",

		       csum);

		ret = -EINVAL;

	}



	for (i = 0; i < size / 4 ; i++) {

		*cache++ = (be32_to_cpu(p[i]) & 0xffff0000) >> 16;

		*cache++ = be32_to_cpu(p[i]) & 0xffff;

	}



	release_firmware(fw);



	return ret;

}



static int upgrade_fw(struct adapter *adap)

{

firmware/Makefile

+4 −1
Original line number Diff line number Diff line
@@ -41,7 +41,10 @@ fw-shipped-$(CONFIG_CASSINI) += sun/cassini.bin 
fw-shipped-$(CONFIG_COMPUTONE) += intelliport2.bin

fw-shipped-$(CONFIG_CHELSIO_T3) += cxgb3/t3b_psram-1.1.0.bin \

				   cxgb3/t3c_psram-1.1.0.bin \

				   cxgb3/t3fw-7.4.0.bin

				   cxgb3/t3fw-7.4.0.bin \

				   cxgb3/ael2005_opt_edc.bin \

				   cxgb3/ael2005_twx_edc.bin \

				   cxgb3/ael2020_twx_edc.bin

fw-shipped-$(CONFIG_DVB_AV7110) += av7110/bootcode.bin

fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin

fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \