Commit 2ebd1036 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Allow subvp on vactive pipes that are 2560x1440@60 



Enable subvp on specifically 1440p@60hz displays even though it can
switch in vactive.

Tested-by: default avatarDaniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 58330ef1

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h

+2 −0
Original line number Diff line number Diff line
@@ -144,6 +144,8 @@ void dcn32_restore_mall_state(struct dc *dc, 
		struct dc_state *context,

		struct mall_temp_config *temp_config);



bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe);



/* definitions for run time init of reg offsets */



/* CLK SRC */

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+30 −1
Original line number Diff line number Diff line
@@ -694,7 +694,9 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc, 
		 */

		if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) &&

				pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120 && !pipe->plane_state->address.tmz_surface &&

				vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) {

				(vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 ||

				(vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&

						dcn32_allow_subvp_with_active_margin(pipe)))) {

			while (pipe) {

				num_pipes++;

				pipe = pipe->bottom_pipe;
@@ -2675,3 +2677,30 @@ void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, 
	pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;

	pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;

}



bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)

{

	bool allow = false;

	uint32_t refresh_rate = 0;



	/* Allow subvp on displays that have active margin for 2560x1440@60hz displays

	 * only for now. There must be no scaling as well.

	 *

	 * For now we only enable on 2560x1440@60hz displays to enable 4K60 + 1440p60 configs

	 * for p-state switching.

	 */

	if (pipe->stream && pipe->plane_state) {

		refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +

						pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)

						/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);

		if (pipe->stream->timing.v_addressable == 1440 &&

				pipe->stream->timing.h_addressable == 2560 &&

				refresh_rate >= 55 && refresh_rate <= 65 &&

				pipe->plane_state->src_rect.height == 1440 &&

				pipe->plane_state->src_rect.width == 2560 &&

				pipe->plane_state->dst_rect.height == 1440 &&

				pipe->plane_state->dst_rect.width == 2560)

			allow = true;

	}

	return allow;

}