Commit 2f383054 authored Nov 17, 2022 by Radhakrishna Sripada Committed by Tvrtko Ursulin Nov 29, 2022

drm/i915/mtl: Fix dram info readout



MEM_SS_INFO_GLOBAL Register info read from the hardware is cached in val. However
the variable is being modified when determining the DRAM type thereby clearing out
the channels and qgv info extracted later in the function xelpdp_get_dram_info. Preserve
the register value and use extracted fields in the switch statement.

Fixes: 825477e7 ("drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox")
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221117213015.584417-1-radhakrishna.sripada@intel.com


(cherry picked from commit ec35c41d)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

parent b7b275e6

drivers/gpu/drm/i915/intel_dram.c

+1 −2

Original line number	Original line	Diff line number	Diff line
	@@ -471,8 +471,7 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915)
	u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);		u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
	struct dram_info *dram_info = &i915->dram_info;		struct dram_info *dram_info = &i915->dram_info;

	val = REG_FIELD_GET(MTL_DDR_TYPE_MASK, val);		switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
	switch (val) {
	case 0:		case 0:
	dram_info->type = INTEL_DRAM_DDR4;		dram_info->type = INTEL_DRAM_DDR4;
	break;		break;