Commit 2f69b1a4 authored by Kevin Hilman's avatar Kevin Hilman
Browse files

Merge branch 'socfpga/soc' into next/soc 

* socfpga/soc:
  ARM: socfpga: support suspend to ram
  ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
  ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
parents 25263186 44fd8c7d

arch/arm/mach-socfpga/Kconfig

+9 −1
Original line number Diff line number Diff line 
config ARCH_SOCFPGA

menuconfig ARCH_SOCFPGA

	bool "Altera SOCFPGA family" if ARCH_MULTI_V7

	select ARCH_SUPPORTS_BIG_ENDIAN

	select ARM_AMBA
@@ -9,3 +9,11 @@ config ARCH_SOCFPGA 
	select HAVE_ARM_SCU

	select HAVE_ARM_TWD if SMP

	select MFD_SYSCON



if ARCH_SOCFPGA

config SOCFPGA_SUSPEND

	bool "Suspend to RAM on SOCFPGA"

	help

	  Select this if you want to enable Suspend-to-RAM on SOCFPGA

	  platforms.

endif

arch/arm/mach-socfpga/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -4,3 +4,4 @@ 


obj-y					:= socfpga.o

obj-$(CONFIG_SMP)	+= headsmp.o platsmp.o

obj-$(CONFIG_SOCFPGA_SUSPEND)	+= pm.o self-refresh.o

arch/arm/mach-socfpga/core.h

+7 −2
Original line number Diff line number Diff line 
/*

 * Copyright 2012 Pavel Machek <pavel@denx.de>

 * Copyright (C) 2012 Altera Corporation

 * Copyright (C) 2012-2015 Altera Corporation

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by
@@ -25,6 +25,8 @@ 
#define SOCFPGA_RSTMGR_MODPERRST	0x14

#define SOCFPGA_RSTMGR_BRGMODRST	0x1c



#define SOCFPGA_A10_RSTMGR_MODMPURST	0x20



/* System Manager bits */

#define RSTMGR_CTRL_SWCOLDRSTREQ	0x1	/* Cold Reset */

#define RSTMGR_CTRL_SWWARMRSTREQ	0x2	/* Warm Reset */
@@ -38,8 +40,11 @@ extern void socfpga_sysmgr_init(void); 


extern void __iomem *sys_manager_base_addr;

extern void __iomem *rst_manager_base_addr;

extern void __iomem *sdr_ctl_base_addr;



u32 socfpga_sdram_self_refresh(u32 sdr_base);

extern unsigned int socfpga_sdram_self_refresh_sz;



extern struct smp_operations socfpga_smp_ops;

extern char secondary_trampoline, secondary_trampoline_end;



extern unsigned long socfpga_cpu1start_addr;

arch/arm/mach-socfpga/platsmp.c

+35 −1
Original line number Diff line number Diff line
@@ -54,6 +54,29 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) 
	return 0;

}



static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle)

{

	int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;



	if (socfpga_cpu1start_addr) {

		writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr +

		       SOCFPGA_A10_RSTMGR_MODMPURST);

		memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);



		writel(virt_to_phys(socfpga_secondary_startup),

		       sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff));



		flush_cache_all();

		smp_wmb();

		outer_clean_range(0, trampoline_size);



		/* This will release CPU #1 out of reset. */

		writel(0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_MODMPURST);

	}



	return 0;

}



static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)

{

	struct device_node *np;
@@ -83,10 +106,21 @@ static void socfpga_cpu_die(unsigned int cpu) 
		cpu_do_idle();

}



struct smp_operations socfpga_smp_ops __initdata = {

static struct smp_operations socfpga_smp_ops __initdata = {

	.smp_prepare_cpus	= socfpga_smp_prepare_cpus,

	.smp_boot_secondary	= socfpga_boot_secondary,

#ifdef CONFIG_HOTPLUG_CPU

	.cpu_die		= socfpga_cpu_die,

#endif

};



static struct smp_operations socfpga_a10_smp_ops __initdata = {

	.smp_prepare_cpus	= socfpga_smp_prepare_cpus,

	.smp_boot_secondary	= socfpga_a10_boot_secondary,

#ifdef CONFIG_HOTPLUG_CPU

	.cpu_die		= socfpga_cpu_die,

#endif

};



CPU_METHOD_OF_DECLARE(socfpga_smp, "altr,socfpga-smp", &socfpga_smp_ops);

CPU_METHOD_OF_DECLARE(socfpga_a10_smp, "altr,socfpga-a10-smp", &socfpga_a10_smp_ops);

arch/arm/mach-socfpga/pm.c

0 → 100644
+149 −0
Original line number Diff line number Diff line 
/*

 *  arch/arm/mach-socfpga/pm.c

 *

 * Copyright (C) 2014-2015 Altera Corporation. All rights reserved.

 *

 * with code from pm-imx6.c

 * Copyright 2011-2014 Freescale Semiconductor, Inc.

 * Copyright 2011 Linaro Ltd.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#include <linux/bitops.h>

#include <linux/genalloc.h>

#include <linux/init.h>

#include <linux/io.h>

#include <linux/of_platform.h>

#include <linux/suspend.h>

#include <asm/suspend.h>

#include <asm/fncpy.h>

#include "core.h"



/* Pointer to function copied to ocram */

static u32 (*socfpga_sdram_self_refresh_in_ocram)(u32 sdr_base);



static int socfpga_setup_ocram_self_refresh(void)

{

	struct platform_device *pdev;

	phys_addr_t ocram_pbase;

	struct device_node *np;

	struct gen_pool *ocram_pool;

	unsigned long ocram_base;

	void __iomem *suspend_ocram_base;

	int ret = 0;



	np = of_find_compatible_node(NULL, NULL, "mmio-sram");

	if (!np) {

		pr_err("%s: Unable to find mmio-sram in dtb\n", __func__);

		return -ENODEV;

	}



	pdev = of_find_device_by_node(np);

	if (!pdev) {

		pr_warn("%s: failed to find ocram device!\n", __func__);

		ret = -ENODEV;

		goto put_node;

	}



	ocram_pool = dev_get_gen_pool(&pdev->dev);

	if (!ocram_pool) {

		pr_warn("%s: ocram pool unavailable!\n", __func__);

		ret = -ENODEV;

		goto put_node;

	}



	ocram_base = gen_pool_alloc(ocram_pool, socfpga_sdram_self_refresh_sz);

	if (!ocram_base) {

		pr_warn("%s: unable to alloc ocram!\n", __func__);

		ret = -ENOMEM;

		goto put_node;

	}



	ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);



	suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,

						socfpga_sdram_self_refresh_sz,

						false);

	if (!suspend_ocram_base) {

		pr_warn("%s: __arm_ioremap_exec failed!\n", __func__);

		ret = -ENOMEM;

		goto put_node;

	}



	/* Copy the code that puts DDR in self refresh to ocram */

	socfpga_sdram_self_refresh_in_ocram =

		(void *)fncpy(suspend_ocram_base,

			      &socfpga_sdram_self_refresh,

			      socfpga_sdram_self_refresh_sz);



	WARN(!socfpga_sdram_self_refresh_in_ocram,

	     "could not copy function to ocram");

	if (!socfpga_sdram_self_refresh_in_ocram)

		ret = -EFAULT;



put_node:

	of_node_put(np);



	return ret;

}



static int socfpga_pm_suspend(unsigned long arg)

{

	u32 ret;



	if (!sdr_ctl_base_addr)

		return -EFAULT;



	ret = socfpga_sdram_self_refresh_in_ocram((u32)sdr_ctl_base_addr);



	pr_debug("%s self-refresh loops request=%d exit=%d\n", __func__,

		 ret & 0xffff, (ret >> 16) & 0xffff);



	return 0;

}



static int socfpga_pm_enter(suspend_state_t state)

{

	switch (state) {

	case PM_SUSPEND_STANDBY:

	case PM_SUSPEND_MEM:

		outer_disable();

		cpu_suspend(0, socfpga_pm_suspend);

		outer_resume();

		break;

	default:

		return -EINVAL;

	}

	return 0;

}



static const struct platform_suspend_ops socfpga_pm_ops = {

	.valid	= suspend_valid_only_mem,

	.enter	= socfpga_pm_enter,

};



static int __init socfpga_pm_init(void)

{

	int ret;



	ret = socfpga_setup_ocram_self_refresh();

	if (ret)

		return ret;



	suspend_set_ops(&socfpga_pm_ops);

	pr_info("SoCFPGA initialized for DDR self-refresh during suspend.\n");



	return 0;

}

arch_initcall(socfpga_pm_init);