Loading arch/arc/mm/tlbex.S +9 −0 Original line number Diff line number Diff line Loading @@ -274,6 +274,13 @@ ex_saved_reg1: .macro COMMIT_ENTRY_TO_MMU #if (CONFIG_ARC_MMU_VER < 4) #ifdef CONFIG_EZNPS_MTM_EXT /* verify if entry for this vaddr+ASID already exists */ sr TLBProbe, [ARC_REG_TLBCOMMAND] lr r0, [ARC_REG_TLBINDEX] bbit0 r0, 31, 88f #endif /* Get free TLB slot: Set = computed from vaddr, way = random */ sr TLBGetIndex, [ARC_REG_TLBCOMMAND] Loading @@ -287,6 +294,8 @@ ex_saved_reg1: #else sr TLBInsertEntry, [ARC_REG_TLBCOMMAND] #endif 88: .endm Loading Loading
arch/arc/mm/tlbex.S +9 −0 Original line number Diff line number Diff line Loading @@ -274,6 +274,13 @@ ex_saved_reg1: .macro COMMIT_ENTRY_TO_MMU #if (CONFIG_ARC_MMU_VER < 4) #ifdef CONFIG_EZNPS_MTM_EXT /* verify if entry for this vaddr+ASID already exists */ sr TLBProbe, [ARC_REG_TLBCOMMAND] lr r0, [ARC_REG_TLBINDEX] bbit0 r0, 31, 88f #endif /* Get free TLB slot: Set = computed from vaddr, way = random */ sr TLBGetIndex, [ARC_REG_TLBCOMMAND] Loading @@ -287,6 +294,8 @@ ex_saved_reg1: #else sr TLBInsertEntry, [ARC_REG_TLBCOMMAND] #endif 88: .endm Loading