Commit 312e95c6 authored Oct 06, 2020 by Lars Povlsen Committed by Sebastian Reichel Oct 08, 2020

dt-bindings: reset: ocelot: Add Sparx5 support



This adds the support for the Sparx5 SoC.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>

parent 8ae237ec

Documentation/devicetree/bindings/power/reset/ocelot-reset.txt

+5 −2

Original line number	Diff line number	Diff line
		Microsemi Ocelot reset controller

		The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
		SoC MIPS core.
		SoC core.

		The reset registers are both present in the MSCC vcoreiii MIPS and
		microchip Sparx5 armv8 SoC's.

		Required Properties:
		- compatible: "mscc,ocelot-chip-reset"
		- compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset"

		Example:
		reset@1070008 {

MAINTAINERS

+1 −0

Original line number	Diff line number	Diff line
		@@ -11515,6 +11515,7 @@ M: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
		L: linux-mips@vger.kernel.org
		S: Supported
		F: Documentation/devicetree/bindings/mips/mscc.txt
		F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
		F: arch/mips/boot/dts/mscc/
		F: arch/mips/configs/generic/board-ocelot.config
		F: arch/mips/generic/board-ocelot.c