Commit 31d64b82 authored by Jimmy Kizito's avatar Jimmy Kizito Committed by Alex Deucher
Browse files

drm/amd/display: Add work around to enforce TBT3 compatibility. 



[Why]
According to the USB4 specification, FEC and DSC should be disabled
when a USB4 DPIA operates in TBT3 compatibility mode.

[How]
Upon detecting that a USB4 DPIA is connected to a device that is known
to operate in TBT3 mode, disable FEC and DSC support if they have been
reported by the TBT3 device.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarMeenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c282d951

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -806,6 +806,7 @@ static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link) 
	if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&

	if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&

			link->type == dc_connection_mst_branch &&

			link->type == dc_connection_mst_branch &&

			link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&

			link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&

			link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 &&

			link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&

			link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&

			!link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)

			!link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)

		link->wa_flags.dpia_mst_dsc_always_on = true;

		link->wa_flags.dpia_mst_dsc_always_on = true;

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+22 −0
Original line number Original line Diff line number Diff line
@@ -5550,6 +5550,28 @@ static bool retrieve_link_cap(struct dc_link *link) 
				link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,

				link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,

				sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));

				sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));

#endif

#endif



		/* Apply work around to disable FEC and DSC for USB4 tunneling in TBT3 compatibility mode

		 * only if required.

		 */

		if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

				!link->dc->debug.dpia_debug.bits.disable_force_tbt3_work_around &&

#endif

				link->dpcd_caps.is_branch_dev &&

				link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&

				link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 &&

				(link->dpcd_caps.fec_cap.bits.FEC_CAPABLE ||

				link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)) {

			/* A TBT3 device is expected to report no support for FEC or DSC to a USB4 DPIA.

			 * Clear FEC and DSC capabilities as a work around if that is not the case.

			 */

			link->wa_flags.dpia_forced_tbt3_mode = true;

			memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps));

			memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));

			DC_LOG_DSC("Clear DSC SUPPORT for USB4 link(%d) in TBT3 compatibility mode", link->link_index);

		} else

			link->wa_flags.dpia_forced_tbt3_mode = false;

	}

	}





	if (!dpcd_read_sink_ext_caps(link))

	if (!dpcd_read_sink_ext_caps(link))

drivers/gpu/drm/amd/display/dc/dc.h

+7 −6
Original line number Original line Diff line number Diff line
@@ -519,12 +519,13 @@ union root_clock_optimization_options { 




union dpia_debug_options {

union dpia_debug_options {

	struct {

	struct {

		uint32_t disable_dpia:1;

		uint32_t disable_dpia:1; /* bit 0 */

		uint32_t force_non_lttpr:1;

		uint32_t force_non_lttpr:1; /* bit 1 */

		uint32_t extend_aux_rd_interval:1;

		uint32_t extend_aux_rd_interval:1; /* bit 2 */

		uint32_t disable_mst_dsc_work_around:1;

		uint32_t disable_mst_dsc_work_around:1; /* bit 3 */

		uint32_t hpd_delay_in_ms:12;

		uint32_t hpd_delay_in_ms:12; /* bits 4-15 */

		uint32_t reserved:16;

		uint32_t disable_force_tbt3_work_around:1; /* bit 16 */

		uint32_t reserved:15;

	} bits;

	} bits;

	uint32_t raw;

	uint32_t raw;

};

};

drivers/gpu/drm/amd/display/dc/dc_link.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -197,6 +197,8 @@ struct dc_link { 
		bool dp_mot_reset_segment;

		bool dp_mot_reset_segment;

		/* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */

		/* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */

		bool dpia_mst_dsc_always_on;

		bool dpia_mst_dsc_always_on;

		/* Forced DPIA into TBT3 compatibility mode. */

		bool dpia_forced_tbt3_mode;

	} wa_flags;

	} wa_flags;

	struct link_mst_stream_allocation_table mst_stream_alloc_table;

	struct link_mst_stream_allocation_table mst_stream_alloc_table;

drivers/gpu/drm/amd/display/include/ddc_service_types.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -34,6 +34,8 @@ 
#define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24

#define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24

#define DP_BRANCH_DEVICE_ID_00E04C 0x00E04C

#define DP_BRANCH_DEVICE_ID_00E04C 0x00E04C

#define DP_BRANCH_DEVICE_ID_006037 0x006037

#define DP_BRANCH_DEVICE_ID_006037 0x006037

#define DP_BRANCH_HW_REV_10 0x10

#define DP_BRANCH_HW_REV_20 0x20





#define DP_DEVICE_ID_38EC11 0x38EC11

#define DP_DEVICE_ID_38EC11 0x38EC11

enum ddc_result {

enum ddc_result {