Commit 31df6df8 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo
Browse files

wifi: rtw89: 8851b: add basic power on function 



Add basic functions to power on chip and enable and access BB/RF, as
well as reset and hardware settings of BB.

Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20230512061220.16544-5-pkshih@realtek.com
parent 4885b17e

drivers/net/wireless/realtek/rtw89/mac.h

+2 −0
Original line number Diff line number Diff line
@@ -1116,6 +1116,8 @@ enum rtw89_mac_xtal_si_offset { 
	XTAL_SI_PWR_CUT = 0x10,

#define XTAL_SI_SMALL_PWR_CUT	BIT(0)

#define XTAL_SI_BIG_PWR_CUT	BIT(1)

	XTAL_SI_XTAL_DRV = 0x15,

#define XTAL_SI_DRV_LATCH	BIT(4)

	XTAL_SI_XTAL_XMD_2 = 0x24,

#define XTAL_SI_LDO_LPS		GENMASK(6, 4)

	XTAL_SI_XTAL_XMD_4 = 0x26,

drivers/net/wireless/realtek/rtw89/reg.h

+17 −0
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@ 
#define B_AX_FEN_BBRSTB BIT(0)



#define R_AX_SYS_PW_CTRL 0x0004

#define B_AX_SOP_ASWRM BIT(31)

#define B_AX_SOP_PWMM_DSWR BIT(29)

#define B_AX_XTAL_OFF_A_DIE BIT(22)

#define B_AX_DIS_WLBT_PDNSUSEN_SOPC BIT(18)

#define B_AX_RDY_SYSPWR BIT(17)
@@ -134,6 +136,8 @@ 
#define B_AX_PLATFORM_EN BIT(0)



#define R_AX_WLLPS_CTRL 0x0090

#define B_AX_LPSOP_ASWRM BIT(17)

#define B_AX_LPSOP_DSWRM BIT(9)

#define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1)

#define SW_LPS_OPTION 0x0001A0B2
@@ -222,9 +226,14 @@ 
#define B_AX_OCP_L1_MASK GENMASK(15, 13)

#define B_AX_VOL_L1_MASK GENMASK(3, 0)



#define R_AX_SPSLDO_ON_CTRL1 0x0204

#define B_AX_FPWMDELAY BIT(3)



#define R_AX_LDO_AON_CTRL0 0x0218

#define B_AX_PD_REGU_L BIT(16)



#define R_AX_SPSANA_ON_CTRL1 0x0224



#define R_AX_WLAN_XTAL_SI_CTRL 0x0270

#define B_AX_WL_XTAL_SI_CMD_POLL BIT(31)

#define B_AX_BT_XTAL_SI_ERR_FLAG BIT(30)
@@ -237,6 +246,9 @@ 
#define B_AX_WL_XTAL_SI_DATA_MASK GENMASK(15, 8)

#define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)



#define R_AX_WLAN_XTAL_SI_CONFIG 0x0274

#define B_AX_XTAL_SI_ADDR_NOT_CHK BIT(0)



#define R_AX_XTAL_ON_CTRL0 0x0280

#define B_AX_XTAL_SC_LPS BIT(31)

#define B_AX_XTAL_SC_XO_MASK GENMASK(23, 17)
@@ -267,6 +279,10 @@ 
#define B_AX_EESK_PULL_LOW_EN BIT(17)

#define B_AX_EECS_PULL_LOW_EN BIT(16)



#define R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN 0x02E4

#define B_AX_GPIO16_PULL_LOW_EN_V1 BIT(19)

#define B_AX_GPIO10_PULL_LOW_EN BIT(10)



#define R_AX_WLRF_CTRL 0x02F0

#define B_AX_AFC_AFEDIG BIT(17)

#define B_AX_WLRF1_CTRL_7 BIT(15)
@@ -4497,6 +4513,7 @@ 
#define B_RFSW_CTRL_ANT_MAPPING GENMASK(15, 0)

#define R_RFE_SEL0_BASE 0x5880

#define B_RFE_SEL0_SRC_MASK GENMASK(3, 0)

#define R_RFE_SEL32_BASE 0x5884

#define RFE_SEL0_SRC_ANTSEL_0 8

#define R_RFE_INV0 0x5890

#define R_P0_RFM 0x5894

drivers/net/wireless/realtek/rtw89/rtw8851b.c

+327 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 */



#include "coex.h"

#include "efuse.h"

#include "fw.h"

#include "mac.h"

#include "phy.h"
@@ -118,6 +119,182 @@ static const struct rtw89_btc_fbtc_mreg rtw89_btc_8851b_mon_reg[] = { 
static const u8 rtw89_btc_8851b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40};

static const u8 rtw89_btc_8851b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};



static int rtw8851b_pwr_on_func(struct rtw89_dev *rtwdev)

{

	u32 val32;

	u8 val8;

	u32 ret;



	rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |

						    B_AX_AFSM_PCIE_SUS_EN);

	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);

	rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);

	rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);

	rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);



	ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,

				1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);

	if (ret)

		return ret;



	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);

	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);



	ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),

				1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);

	if (ret)

		return ret;



	rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);

	rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);

	rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);

	rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);



	rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);

	rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);



	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,

				      XTAL_SI_OFF_WEI);

	if (ret)

		return ret;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,

				      XTAL_SI_OFF_EI);

	if (ret)

		return ret;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);

	if (ret)

		return ret;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,

				      XTAL_SI_PON_WEI);

	if (ret)

		return ret;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,

				      XTAL_SI_PON_EI);

	if (ret)

		return ret;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);

	if (ret)

		return ret;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);

	if (ret)

		return ret;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);

	if (ret)

		return ret;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);

	if (ret)

		return ret;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_DRV, 0, XTAL_SI_DRV_LATCH);

	if (ret)

		return ret;



	rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);

	rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);

	rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);



	fsleep(1000);



	rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);

	rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);

	rtw89_write32_set(rtwdev, R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN,

			  B_AX_GPIO10_PULL_LOW_EN | B_AX_GPIO16_PULL_LOW_EN_V1);



	if (rtwdev->hal.cv == CHIP_CAV) {

		ret = rtw89_read_efuse_ver(rtwdev, &val8);

		if (!ret)

			rtwdev->hal.cv = val8;

	}



	rtw89_write32_clr(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,

			  B_AX_XTAL_SI_ADDR_NOT_CHK);

	if (rtwdev->hal.cv != CHIP_CAV) {

		rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);

		rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);

	}



	rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,

			  B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |

			  B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |

			  B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |

			  B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |

			  B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |

			  B_AX_DMACREG_GCKEN);

	rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,

			  B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |

			  B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN |

			  B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN |

			  B_AX_RMAC_EN);



	rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,

			   PINMUX_EESK_FUNC_SEL_BT_LOG);



	return 0;

}



static void rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev *rtwdev)

{

	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_PWMM_DSWR);

	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_ASWRM);

	rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_DSWRM);

	rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_ASWRM);

}



static int rtw8851b_pwr_off_func(struct rtw89_dev *rtwdev)

{

	u32 val32;

	u32 ret;



	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,

				      XTAL_SI_RFC2RF);

	if (ret)

		return ret;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);

	if (ret)

		return ret;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);

	if (ret)

		return ret;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);

	if (ret)

		return ret;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,

				      XTAL_SI_SRAM2RFC);

	if (ret)

		return ret;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);

	if (ret)

		return ret;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);

	if (ret)

		return ret;



	rtw89_write32_set(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,

			  B_AX_XTAL_SI_ADDR_NOT_CHK);

	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);

	rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);

	rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);



	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);



	ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),

				1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);

	if (ret)

		return ret;



	rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);



	if (rtwdev->hal.cv == CHIP_CAV) {

		rtw8851b_patch_swr_pfm2pwm(rtwdev);

	} else {

		rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);

		rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);

	}



	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);



	return 0;

}



static void rtw8851b_set_bb_gpio(struct rtw89_dev *rtwdev, u8 gpio_idx, bool inv,

				 u8 src_sel)

{
@@ -181,6 +358,96 @@ static void rtw8851b_rfe_gpio(struct rtw89_dev *rtwdev) 
	}

}



static void rtw8851b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)

{

	rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);

	fsleep(1);

	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);

	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);

	rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);

	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);

}



static void rtw8851b_bb_reset(struct rtw89_dev *rtwdev,

			      enum rtw89_phy_idx phy_idx)

{

	rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,

			       B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x1);

	rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);

	rtw8851b_bb_reset_all(rtwdev, phy_idx);

	rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,

			       B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x3);

	rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);

}



static

void rtw8851b_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,

			   u8 tx_path_en, u8 trsw_tx,

			   u8 trsw_rx, u8 trsw_a, u8 trsw_b)

{

	u32 mask_ofst = 16;

	u32 val;



	if (path != RF_PATH_A)

		return;



	mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2;

	val = u32_encode_bits(trsw_a, B_P0_TRSW_A) |

	      u32_encode_bits(trsw_b, B_P0_TRSW_B);



	rtw89_phy_write32_mask(rtwdev, R_P0_TRSW,

			       (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val);

}



static void rtw8851b_bb_gpio_init(struct rtw89_dev *rtwdev)

{

	rtw89_phy_write32_set(rtwdev, R_P0_TRSW, B_P0_TRSW_A);

	rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_X);

	rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_SO_A2);

	rtw89_phy_write32(rtwdev, R_RFE_SEL0_BASE, 0x77777777);

	rtw89_phy_write32(rtwdev, R_RFE_SEL32_BASE, 0x77777777);



	rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);

	rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);

	rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);

	rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);



	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);

	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);

	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);

	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);

	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);

	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);

	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);

	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);

}



static void rtw8851b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,

					enum rtw89_phy_idx phy_idx)

{

	u32 addr;



	for (addr = R_AX_PWR_MACID_LMT_TABLE0;

	     addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)

		rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);

}



static void rtw8851b_bb_sethw(struct rtw89_dev *rtwdev)

{

	struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;



	rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);



	rtw8851b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);

	rtw8851b_bb_gpio_init(rtwdev);



	/* read these registers after loading BB parameters */

	gain->offset_base[RTW89_PHY_0] =

		rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);

	gain->rssi_base[RTW89_PHY_0] =

		rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);

}



static void rtw8851b_btc_set_rfe(struct rtw89_dev *rtwdev)

{

	struct rtw89_btc *btc = &rtwdev->btc;
@@ -472,9 +739,69 @@ static void rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 
	}

}



static int rtw8851b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)

{

	int ret;



	rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,

			 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);

	rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);

	rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);

	rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);



	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7,

				      FULL_BIT_MASK);

	if (ret)

		return ret;



	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7,

				      FULL_BIT_MASK);

	if (ret)

		return ret;



	rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);



	return 0;

}



static int rtw8851b_mac_disable_bb_rf(struct rtw89_dev *rtwdev)

{

	u8 wl_rfc_s0;

	u8 wl_rfc_s1;

	int ret;



	rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,

			 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);



	ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);

	if (ret)

		return ret;

	wl_rfc_s0 &= ~XTAL_SI_RF00S_EN;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0,

				      FULL_BIT_MASK);

	if (ret)

		return ret;



	ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);

	if (ret)

		return ret;

	wl_rfc_s1 &= ~XTAL_SI_RF10S_EN;

	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1,

				      FULL_BIT_MASK);

	return ret;

}



static const struct rtw89_chip_ops rtw8851b_chip_ops = {

	.enable_bb_rf		= rtw8851b_mac_enable_bb_rf,

	.disable_bb_rf		= rtw8851b_mac_disable_bb_rf,

	.bb_reset		= rtw8851b_bb_reset,

	.bb_sethw		= rtw8851b_bb_sethw,

	.read_rf		= rtw89_phy_read_rf_v1,

	.write_rf		= rtw89_phy_write_rf_v1,

	.fem_setup		= NULL,

	.rfe_gpio		= rtw8851b_rfe_gpio,

	.pwr_on_func		= rtw8851b_pwr_on_func,

	.pwr_off_func		= rtw8851b_pwr_off_func,

	.fill_txdesc		= rtw89_core_fill_txdesc,

	.fill_txdesc_fwcmd	= rtw89_core_fill_txdesc,

	.h2c_dctl_sec_cam	= NULL,