Commit 3286f88f authored by Kajol Jain's avatar Kajol Jain Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Update the JSON/events descriptions for power10 platform 



Update the description for some of the JSON/events for power10 platform.

Fixes: 32daa5d7 ("perf vendor events: Initial JSON/events list for power10 platform")
Signed-off-by: default avatarKajol Jain <kjain@linux.ibm.com>
Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Cc: Disha Goel <disgoel@linux.ibm.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: linuxppc-dev@lists.ozlabs.org
Link: https://lore.kernel.org/r/20230814112803.1508296-1-kjain@linux.ibm.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 10da1b8e

tools/perf/pmu-events/arch/powerpc/power10/cache.json

+2 −2
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 
  {

    "EventCode": "0x34056",

    "EventName": "PM_EXEC_STALL_LOAD_FINISH",

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the NTF instruction merged with another load in the LMQ; cycles in which the NTF instruction is waiting for a data reload for a load miss, but the data comes back with a non-NTF instruction."

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the next-to-finish (NTF) instruction merged with another load in the LMQ; cycles in which the NTF instruction is waiting for a data reload for a load miss, but the data comes back with a non-NTF instruction."

  },

  {

    "EventCode": "0x3006C",
@@ -27,7 +27,7 @@ 
  {

    "EventCode": "0x300F4",

    "EventName": "PM_RUN_INST_CMPL_CONC",

    "BriefDescription": "PowerPC instructions completed by this thread when all threads in the core had the run-latch set."

    "BriefDescription": "PowerPC instruction completed by this thread when all threads in the core had the run-latch set."

  },

  {

    "EventCode": "0x4C016",

tools/perf/pmu-events/arch/powerpc/power10/frontend.json

+15 −15
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ 
  {

    "EventCode": "0x10006",

    "EventName": "PM_DISP_STALL_HELD_OTHER_CYC",

    "BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any other reason."

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch for any other reason."

  },

  {

    "EventCode": "0x10010",
@@ -32,12 +32,12 @@ 
  {

    "EventCode": "0x1D05E",

    "EventName": "PM_DISP_STALL_HELD_HALT_CYC",

    "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because of power management."

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because of power management."

  },

  {

    "EventCode": "0x1E050",

    "EventName": "PM_DISP_STALL_HELD_STF_MAPPER_CYC",

    "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR."

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR."

  },

  {

    "EventCode": "0x1F054",
@@ -67,7 +67,7 @@ 
  {

    "EventCode": "0x100F6",

    "EventName": "PM_IERAT_MISS",

    "BriefDescription": "IERAT Reloaded to satisfy an IERAT miss. All page sizes are counted by this event."

    "BriefDescription": "IERAT Reloaded to satisfy an IERAT miss. All page sizes are counted by this event. This event only counts instruction demand access."

  },

  {

    "EventCode": "0x100F8",
@@ -77,7 +77,7 @@ 
  {

    "EventCode": "0x20006",

    "EventName": "PM_DISP_STALL_HELD_ISSQ_FULL_CYC",

    "BriefDescription": "Cycles in which the NTC instruction is held at dispatch due to Issue queue full. Includes issue queue and branch queue."

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch due to Issue queue full. Includes issue queue and branch queue."

  },

  {

    "EventCode": "0x20114",
@@ -102,7 +102,7 @@ 
  {

    "EventCode": "0x2D01A",

    "EventName": "PM_DISP_STALL_IC_MISS",

    "BriefDescription": "Cycles when dispatch was stalled for this thread due to an Icache Miss."

    "BriefDescription": "Cycles when dispatch was stalled for this thread due to an instruction cache miss."

  },

  {

    "EventCode": "0x2E018",
@@ -112,7 +112,7 @@ 
  {

    "EventCode": "0x2E01A",

    "EventName": "PM_DISP_STALL_HELD_XVFC_MAPPER_CYC",

    "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the XVFC mapper/SRB was full."

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the XVFC mapper/SRB was full."

  },

  {

    "EventCode": "0x2C142",
@@ -137,7 +137,7 @@ 
  {

    "EventCode": "0x30004",

    "EventName": "PM_DISP_STALL_FLUSH",

    "BriefDescription": "Cycles when dispatch was stalled because of a flush that happened to an instruction(s) that was not yet NTC. PM_EXEC_STALL_NTC_FLUSH only includes instructions that were flushed after becoming NTC."

    "BriefDescription": "Cycles when dispatch was stalled because of a flush that happened to an instruction(s) that was not yet next-to-complete (NTC). PM_EXEC_STALL_NTC_FLUSH only includes instructions that were flushed after becoming NTC."

  },

  {

    "EventCode": "0x3000A",
@@ -157,7 +157,7 @@ 
  {

    "EventCode": "0x30018",

    "EventName": "PM_DISP_STALL_HELD_SCOREBOARD_CYC",

    "BriefDescription": "Cycles in which the NTC instruction is held at dispatch while waiting on the Scoreboard. This event combines VSCR and FPSCR together."

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch while waiting on the Scoreboard. This event combines VSCR and FPSCR together."

  },

  {

    "EventCode": "0x30026",
@@ -182,7 +182,7 @@ 
  {

    "EventCode": "0x3D05C",

    "EventName": "PM_DISP_STALL_HELD_RENAME_CYC",

    "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR and XVFC."

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR and XVFC."

  },

  {

    "EventCode": "0x3E052",
@@ -192,7 +192,7 @@ 
  {

    "EventCode": "0x3E054",

    "EventName": "PM_LD_MISS_L1",

    "BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."

    "BriefDescription": "Load missed L1, counted at finish time. LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."

  },

  {

    "EventCode": "0x301EA",
@@ -202,7 +202,7 @@ 
  {

    "EventCode": "0x300FA",

    "EventName": "PM_INST_FROM_L3MISS",

    "BriefDescription": "The processor's instruction cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss."

    "BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss."

  },

  {

    "EventCode": "0x40006",
@@ -232,16 +232,16 @@ 
  {

    "EventCode": "0x4E01A",

    "EventName": "PM_DISP_STALL_HELD_CYC",

    "BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any reason."

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch for any reason."

  },

  {

    "EventCode": "0x4003C",

    "EventName": "PM_DISP_STALL_HELD_SYNC_CYC",

    "BriefDescription": "Cycles in which the NTC instruction is held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch."

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch."

  },

  {

    "EventCode": "0x44056",

    "EventName": "PM_VECTOR_ST_CMPL",

    "BriefDescription": "Vector store instructions completed."

    "BriefDescription": "Vector store instruction completed."

  }

]

tools/perf/pmu-events/arch/powerpc/power10/marked.json

+10 −10
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ 
  {

    "EventCode": "0x200FD",

    "EventName": "PM_L1_ICACHE_MISS",

    "BriefDescription": "Demand iCache Miss."

    "BriefDescription": "Demand instruction cache miss."

  },

  {

    "EventCode": "0x30130",
@@ -72,7 +72,7 @@ 
  {

    "EventCode": "0x34146",

    "EventName": "PM_MRK_LD_CMPL",

    "BriefDescription": "Marked loads completed."

    "BriefDescription": "Marked load instruction completed."

  },

  {

    "EventCode": "0x3E158",
@@ -82,12 +82,12 @@ 
  {

    "EventCode": "0x3E15A",

    "EventName": "PM_MRK_ST_FIN",

    "BriefDescription": "The marked instruction was a store of any kind."

    "BriefDescription": "Marked store instruction finished."

  },

  {

    "EventCode": "0x30068",

    "EventName": "PM_L1_ICACHE_RELOADED_PREF",

    "BriefDescription": "Counts all Icache prefetch reloads ( includes demand turned into prefetch)."

    "BriefDescription": "Counts all instruction cache prefetch reloads (includes demand turned into prefetch)."

  },

  {

    "EventCode": "0x301E4",
@@ -102,12 +102,12 @@ 
  {

    "EventCode": "0x300FE",

    "EventName": "PM_DATA_FROM_L3MISS",

    "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss."

    "BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss."

  },

  {

    "EventCode": "0x40012",

    "EventName": "PM_L1_ICACHE_RELOADED_ALL",

    "BriefDescription": "Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch."

    "BriefDescription": "Counts all instruction cache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch."

  },

  {

    "EventCode": "0x40134",
@@ -117,22 +117,22 @@ 
  {

    "EventCode": "0x4505A",

    "EventName": "PM_SP_FLOP_CMPL",

    "BriefDescription": "Single Precision floating point instructions completed."

    "BriefDescription": "Single Precision floating point instruction completed."

  },

  {

    "EventCode": "0x4D058",

    "EventName": "PM_VECTOR_FLOP_CMPL",

    "BriefDescription": "Vector floating point instructions completed."

    "BriefDescription": "Vector floating point instruction completed."

  },

  {

    "EventCode": "0x4D05A",

    "EventName": "PM_NON_MATH_FLOP_CMPL",

    "BriefDescription": "Non Math instructions completed."

    "BriefDescription": "Non Math instruction completed."

  },

  {

    "EventCode": "0x401E0",

    "EventName": "PM_MRK_INST_CMPL",

    "BriefDescription": "marked instruction completed."

    "BriefDescription": "Marked instruction completed."

  },

  {

    "EventCode": "0x400FE",

tools/perf/pmu-events/arch/powerpc/power10/memory.json

+3 −3
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ 
  {

    "EventCode": "0x10062",

    "EventName": "PM_LD_L3MISS_PEND_CYC",

    "BriefDescription": "Cycles L3 miss was pending for this thread."

    "BriefDescription": "Cycles in which an L3 miss was pending for this thread."

  },

  {

    "EventCode": "0x20010",
@@ -132,7 +132,7 @@ 
  {

    "EventCode": "0x300FC",

    "EventName": "PM_DTLB_MISS",

    "BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. It includes pages of all sizes for demand and prefetch activity."

    "BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. This event only counts for demand misses."

  },

  {

    "EventCode": "0x4D02C",
@@ -142,7 +142,7 @@ 
  {

    "EventCode": "0x4003E",

    "EventName": "PM_LD_CMPL",

    "BriefDescription": "Loads completed."

    "BriefDescription": "Load instruction completed."

  },

  {

    "EventCode": "0x4C040",

tools/perf/pmu-events/arch/powerpc/power10/others.json

+24 −24
Original line number Diff line number Diff line
@@ -2,12 +2,12 @@ 
  {

    "EventCode": "0x10016",

    "EventName": "PM_VSU0_ISSUE",

    "BriefDescription": "VSU instructions issued to VSU pipe 0."

    "BriefDescription": "VSU instruction issued to VSU pipe 0."

  },

  {

    "EventCode": "0x1001C",

    "EventName": "PM_ULTRAVISOR_INST_CMPL",

    "BriefDescription": "PowerPC instructions that completed while the thread was in ultravisor state."

    "BriefDescription": "PowerPC instruction completed while the thread was in ultravisor state."

  },

  {

    "EventCode": "0x100F0",
@@ -17,12 +17,12 @@ 
  {

    "EventCode": "0x10134",

    "EventName": "PM_MRK_ST_DONE_L2",

    "BriefDescription": "Marked stores completed in L2 (RC machine done)."

    "BriefDescription": "Marked store completed in L2."

  },

  {

    "EventCode": "0x1505E",

    "EventName": "PM_LD_HIT_L1",

    "BriefDescription": "Loads that finished without experiencing an L1 miss."

    "BriefDescription": "Load finished without experiencing an L1 miss."

  },

  {

    "EventCode": "0x1F056",
@@ -42,7 +42,7 @@ 
  {

    "EventCode": "0x101E4",

    "EventName": "PM_MRK_L1_ICACHE_MISS",

    "BriefDescription": "Marked Instruction suffered an icache Miss."

    "BriefDescription": "Marked instruction suffered an instruction cache miss."

  },

  {

    "EventCode": "0x101EA",
@@ -72,7 +72,7 @@ 
  {

    "EventCode": "0x2E010",

    "EventName": "PM_ADJUNCT_INST_CMPL",

    "BriefDescription": "PowerPC instructions that completed while the thread is in Adjunct state."

    "BriefDescription": "PowerPC instruction completed while the thread was in Adjunct state."

  },

  {

    "EventCode": "0x2E014",
@@ -122,7 +122,7 @@ 
  {

    "EventCode": "0x201E4",

    "EventName": "PM_MRK_DATA_FROM_L3MISS",

    "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss for a marked load."

    "BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction."

  },

  {

    "EventCode": "0x201E8",
@@ -132,17 +132,17 @@ 
  {

    "EventCode": "0x200F2",

    "EventName": "PM_INST_DISP",

    "BriefDescription": "PowerPC instructions dispatched."

    "BriefDescription": "PowerPC instruction dispatched."

  },

  {

    "EventCode": "0x30132",

    "EventName": "PM_MRK_VSU_FIN",

    "BriefDescription": "VSU marked instructions finished. Excludes simple FX instructions issued to the Store Unit."

    "BriefDescription": "VSU marked instruction finished. Excludes simple FX instructions issued to the Store Unit."

  },

  {

    "EventCode": "0x30038",

    "EventName": "PM_EXEC_STALL_DMISS_LMEM",

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local memory, local OpenCapp cache, or local OpenCapp memory."

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local memory, local OpenCAPI cache, or local OpenCAPI memory."

  },

  {

    "EventCode": "0x3F04A",
@@ -152,12 +152,12 @@ 
  {

    "EventCode": "0x3405A",

    "EventName": "PM_PRIVILEGED_INST_CMPL",

    "BriefDescription": "PowerPC Instructions that completed while the thread is in Privileged state."

    "BriefDescription": "PowerPC instruction completed while the thread was in Privileged state."

  },

  {

    "EventCode": "0x3F150",

    "EventName": "PM_MRK_ST_DRAIN_CYC",

    "BriefDescription": "cycles to drain st from core to L2."

    "BriefDescription": "Cycles in which the marked store drained from the core to the L2."

  },

  {

    "EventCode": "0x3F054",
@@ -182,7 +182,7 @@ 
  {

    "EventCode": "0x4001C",

    "EventName": "PM_VSU_FIN",

    "BriefDescription": "VSU instructions finished."

    "BriefDescription": "VSU instruction finished."

  },

  {

    "EventCode": "0x4C01A",
@@ -197,7 +197,7 @@ 
  {

    "EventCode": "0x4D022",

    "EventName": "PM_HYPERVISOR_INST_CMPL",

    "BriefDescription": "PowerPC instructions that completed while the thread is in hypervisor state."

    "BriefDescription": "PowerPC instruction completed while the thread was in hypervisor state."

  },

  {

    "EventCode": "0x4D026",
@@ -212,32 +212,32 @@ 
  {

    "EventCode": "0x40030",

    "EventName": "PM_INST_FIN",

    "BriefDescription": "Instructions finished."

    "BriefDescription": "Instruction finished."

  },

  {

    "EventCode": "0x44146",

    "EventName": "PM_MRK_STCX_CORE_CYC",

    "BriefDescription": "Cycles spent in the core portion of a marked Stcx instruction. It starts counting when the instruction is decoded and stops counting when it drains into the L2."

    "BriefDescription": "Cycles spent in the core portion of a marked STCX instruction. It starts counting when the instruction is decoded and stops counting when it drains into the L2."

  },

  {

    "EventCode": "0x44054",

    "EventName": "PM_VECTOR_LD_CMPL",

    "BriefDescription": "Vector load instructions completed."

    "BriefDescription": "Vector load instruction completed."

  },

  {

    "EventCode": "0x45054",

    "EventName": "PM_FMA_CMPL",

    "BriefDescription": "Two floating point instructions completed (FMA class of instructions: fmadd, fnmadd, fmsub, fnmsub). Scalar instructions only."

    "BriefDescription": "Two floating point instruction completed (FMA class of instructions: fmadd, fnmadd, fmsub, fnmsub). Scalar instructions only."

  },

  {

    "EventCode": "0x45056",

    "EventName": "PM_SCALAR_FLOP_CMPL",

    "BriefDescription": "Scalar floating point instructions completed."

    "BriefDescription": "Scalar floating point instruction completed."

  },

  {

    "EventCode": "0x4505C",

    "EventName": "PM_MATH_FLOP_CMPL",

    "BriefDescription": "Math floating point instructions completed."

    "BriefDescription": "Math floating point instruction completed."

  },

  {

    "EventCode": "0x4D05E",
@@ -252,21 +252,21 @@ 
  {

    "EventCode": "0x401E6",

    "EventName": "PM_MRK_INST_FROM_L3MISS",

    "BriefDescription": "The processor's instruction cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss for a marked instruction."

    "BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction."

  },

  {

    "EventCode": "0x401E8",

    "EventName": "PM_MRK_DATA_FROM_L2MISS",

    "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1 or L2 due to a demand miss for a marked load."

    "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction."

  },

  {

    "EventCode": "0x400F0",

    "EventName": "PM_LD_DEMAND_MISS_L1_FIN",

    "BriefDescription": "Load Missed L1, counted at finish time."

    "BriefDescription": "Load missed L1, counted at finish time."

  },

  {

    "EventCode": "0x500FA",

    "EventName": "PM_RUN_INST_CMPL",

    "BriefDescription": "Completed PowerPC instructions gated by the run latch."

    "BriefDescription": "PowerPC instruction completed while the run latch is set."

  }

]