Commit 33137187 authored by Fabio Aiuto's avatar Fabio Aiuto Committed by Greg Kroah-Hartman
Browse files

staging: rtl8723bs: remove code related to unsupported channel bandwidth 



remove all code related to unsupported channel
bandwidth (i.e. 80, 80+80, 160 Mhz). rtl8723bs NIC
works only on 20 and 40 Mhz channels.

Module parameter rtw_bw_mode can only have two
values: 0 and 1 (20 Mhz and 40Mhz). So modify
the default value setting to zero the 5Ghz nibble.

Comments modified accordingly.

Acked-by: default avatarHans de Goede <hdegoede@redhat.com>
Signed-off-by: default avatarFabio Aiuto <fabioaiuto83@gmail.com>
Link: https://lore.kernel.org/r/7b2ee7cc0abfd8744ed5ff4a654fb333fee77ec7.1624367071.git.fabioaiuto83@gmail.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 708180a9

drivers/staging/rtl8723bs/core/rtw_wlan_util.c

+1 −14
Original line number Diff line number Diff line
@@ -336,9 +336,7 @@ u8 rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset) 
{

	u8 center_ch = channel;



	if (chnl_bw == CHANNEL_WIDTH_80) {

		center_ch = 7;

	} else if (chnl_bw == CHANNEL_WIDTH_40) {

	if (chnl_bw == CHANNEL_WIDTH_40) {

		if (chnl_offset == HAL_PRIME_CHNL_OFFSET_LOWER)

			center_ch = channel + 2;

		else
@@ -375,14 +373,6 @@ void set_channel_bwmode(struct adapter *padapter, unsigned char channel, unsigne 


	center_ch = rtw_get_center_ch(channel, bwmode, channel_offset);



	if (bwmode == CHANNEL_WIDTH_80) {

		if (center_ch > channel)

			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;

		else if (center_ch < channel)

			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;

		else

			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;

	}



	/* set Channel */

	if (mutex_lock_interruptible(&(adapter_to_dvobj(padapter)->setch_mutex)))
@@ -919,9 +909,6 @@ static void bwmode_update_check(struct adapter *padapter, struct ndis_80211_var_ 
	if (phtpriv->ht_option == false)

		return;



	if (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_80)

		return;



	if (pIE->Length > sizeof(struct HT_info_element))

		return;

drivers/staging/rtl8723bs/core/rtw_xmit.c

+1 −4
Original line number Diff line number Diff line
@@ -321,15 +321,12 @@ void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv) 


u8 query_ra_short_GI(struct sta_info *psta)

{

	u8 sgi = false, sgi_20m = false, sgi_40m = false, sgi_80m = false;

	u8 sgi = false, sgi_20m = false, sgi_40m = false;



	sgi_20m = psta->htpriv.sgi_20m;

	sgi_40m = psta->htpriv.sgi_40m;



	switch (psta->bw_mode) {

	case CHANNEL_WIDTH_80:

		sgi = sgi_80m;

		break;

	case CHANNEL_WIDTH_40:

		sgi = sgi_40m;

		break;

drivers/staging/rtl8723bs/hal/hal_com_phycfg.c

+0 −34
Original line number Diff line number Diff line
@@ -995,7 +995,6 @@ u8 PHY_GetTxPowerIndexBase( 
)

{

	struct hal_com_data *pHalData = GET_HAL_DATA(padapter);

	u8 i = 0;	/* default set to 1S */

	u8 txPower = 0;

	u8 chnlIdx = (Channel-1);
@@ -1035,18 +1034,6 @@ u8 PHY_GetTxPowerIndexBase( 
				txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S];



		}

		/*  Willis suggest adopt BW 40M power index while in BW 80 mode */

		else if (BandWidth == CHANNEL_WIDTH_80) {

			if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))

				txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S];

			if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))

				txPower += pHalData->BW40_24G_Diff[RFPath][TX_2S];

			if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))

				txPower += pHalData->BW40_24G_Diff[RFPath][TX_3S];

			if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))

				txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S];



		}

	} else {/* 3 ============================== 5 G ============================== */

		if (MGN_6M <= Rate)

			txPower = pHalData->Index5G_BW40_Base[RFPath][chnlIdx];
@@ -1076,23 +1063,6 @@ u8 PHY_GetTxPowerIndexBase( 
			if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))

				txPower += pHalData->BW40_5G_Diff[RFPath][TX_4S];



		} else if (BandWidth == CHANNEL_WIDTH_80) { /*  BW80-1S, BW80-2S */

			/*  <20121220, Kordan> Get the index of array "Index5G_BW80_Base". */

			u8 channel5G_80M[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};

			for (i = 0; i < ARRAY_SIZE(channel5G_80M); ++i)

				if (channel5G_80M[i] == Channel)

					chnlIdx = i;



			txPower = pHalData->Index5G_BW80_Base[RFPath][chnlIdx];



			if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31)  || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))

				txPower += + pHalData->BW80_5G_Diff[RFPath][TX_1S];

			if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))

				txPower += pHalData->BW80_5G_Diff[RFPath][TX_2S];

			if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))

				txPower += pHalData->BW80_5G_Diff[RFPath][TX_3S];

			if ((MGN_MCS23 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))

				txPower += pHalData->BW80_5G_Diff[RFPath][TX_4S];

		}

	}
@@ -1512,10 +1482,6 @@ static s16 get_bandwidth_idx(const enum channel_width bandwidth) 
		return 0;

	case CHANNEL_WIDTH_40:

		return 1;

	case CHANNEL_WIDTH_80:

		return 2;

	case CHANNEL_WIDTH_160:

		return 3;

	default:

		return -1;

	}

drivers/staging/rtl8723bs/hal/odm.h

+0 −3
Original line number Diff line number Diff line
@@ -471,9 +471,6 @@ enum { /* tag_Band_Type_Definition */ 
enum { /* tag_Bandwidth_Definition */

	ODM_BW20M		= 0,

	ODM_BW40M		= 1,

	ODM_BW80M		= 2,

	ODM_BW160M		= 3,

	ODM_BW10M		= 4,

};



/*  ODM_CMNINFO_BOARD_TYPE */

drivers/staging/rtl8723bs/hal/odm_DIG.c

+0 −2
Original line number Diff line number Diff line
@@ -230,8 +230,6 @@ void odm_Adaptivity(void *pDM_VOID, u8 IGI) 
		IGI_target = pDM_Odm->IGI_Base;

	else if (*pDM_Odm->pBandWidth == ODM_BW40M)

		IGI_target = pDM_Odm->IGI_Base + 2;

	else if (*pDM_Odm->pBandWidth == ODM_BW80M)

		IGI_target = pDM_Odm->IGI_Base + 2;

	else

		IGI_target = pDM_Odm->IGI_Base;

	pDM_Odm->IGI_target = (u8) IGI_target;