Unverified Commit 33f8b486 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-dt64-5.17' of... 

Merge tag 'imx-dt64-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm64 device tree change for 5.17:

- New SoC support: i.MX8 ULP.
- New board support: i.MX8MM/MN based TQMa8Mx boards, iMX8MN BSH SMM S2,
  i.MX8 ULP EVK.
- A series from Adam Ford to enable Camera and USB support for
  imx8mm-beacon device.
- Add overlays for various serdes protocols on LS1028A QDS board using
  different PHY cards.
- A series from Biwen Li to update LS1028A devices around RTC, flextimer
  and PWM support.
- A series from Joakim Zhang to update ENET/FEC suppport on i.MX8M
  devices.
- A couple of changes from Lucas Stach to update nitrogen8-som Ethernet
  PHY and I2C1 pad configuration.
- A series from Martin Kepplinger to split out a shared imx8mq-librem5-r3
  dtsi for Librem5 devices.
- Add cache descriptions for i.MX8 SoCs.
- A series from Vladimir Oltean to update ls1028a-rdb device tree in
  order to share the DTS between Linux and U-Boot.
- Random device addtion to various i.MX8 and LX2160A based devices.

* tag 'imx-dt64-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (56 commits)
  arm64: dts: imx8mp-evk: configure multiple queues on eqos
  arm64: dts: ls1028a-qds: add overlays for various serdes protocols
  arm64: dts: ls1028a-qds: enable lpuart1
  arm64: dts: ls1028a-qds: move rtc node to the correct i2c bus
  arm64: dts: ls1028a-rdb: enable pwm0
  arm64: dts: ls1028a: add flextimer based pwm nodes
  arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source
  arm64: dts: ls1028a: Add PCIe EP nodes
  arm64: dts: lx2162a-qds: add interrupt line for RTC node
  arm64: dts: lx2162a-qds: support SD UHS-I and eMMC HS400 modes
  arm64: dts: lx2160a: enable usb3-lpm-capable for usb3 nodes
  arm64: dts: lx2160a-qds: Add mdio mux nodes
  arm64: dts: lx2160a: add optee-tz node
  arm64: dts: lx2160a-rdb: Add Inphi PHY node
  arm64: dts: imx8mm: don't assign PLL2 in SoC dtsi
  arm64: dts: nitrogen8-som: correct i2c1 pad-ctrl
  arm64: dts: nitrogen8-som: correct network PHY reset
  arm64: dts: imx8mn-bsh-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
  arm64: dts: imx8mm/n: Remove the 'pm-ignore-notify' property
  arm64: dts: imx8ulp: add power domain entry for usdhc
  ...

Link: https://lore.kernel.org/r/20211218071427.26745-5-shawnguo@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents a5a44f4d 0bc3e333

arch/arm64/boot/dts/freescale/Makefile

+22 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0



# required for overlay support

DTC_FLAGS_fsl-ls1028a-qds := -@

DTC_FLAGS_fsl-ls1028a-qds-13bb := -@

DTC_FLAGS_fsl-ls1028a-qds-65bb := -@

DTC_FLAGS_fsl-ls1028a-qds-7777 := -@

DTC_FLAGS_fsl-ls1028a-qds-85bb := -@

DTC_FLAGS_fsl-ls1028a-qds-899b := -@

DTC_FLAGS_fsl-ls1028a-qds-9999 := -@



dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb
@@ -11,6 +21,12 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb 
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb

dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
@@ -40,6 +56,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb 
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb
@@ -47,8 +64,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb 
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
@@ -60,6 +80,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb 
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r4.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mq-tqma8mq-mba8mx.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mq-mnt-reform2.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mq-phanbell.dtb
@@ -71,6 +92,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb 
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb



dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb

dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb

arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts

0 → 100644
+113 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Device Tree fragment for LS1028A QDS board, serdes 13bb

 *

 * Copyright 2019-2021 NXP

 *

 * Requires a LS1028A QDS board with lane B rework.

 * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.

 * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.

 */



/dts-v1/;

/plugin/;



/ {

	fragment@0 {

		target = <&mdio_slot1>;



		__overlay__ {

			#address-cells = <1>;

			#size-cells = <0>;



			slot1_sgmii: ethernet-phy@2 {

				/* AQR112 */

				reg = <0x2>;

				compatible = "ethernet-phy-ieee802.3-c45";

			};

		};

	};



	fragment@1 {

		target = <&enetc_port0>;



		__overlay__ {

			phy-handle = <&slot1_sgmii>;

			phy-mode = "usxgmii";

			managed = "in-band-status";

			status = "okay";

		};

	};



	fragment@2 {

		target = <&mdio_slot2>;



		__overlay__ {

			#address-cells = <1>;

			#size-cells = <0>;



			/* 4 ports on AQR412 */

			slot2_qxgmii0: ethernet-phy@0 {

				reg = <0x0>;

				compatible = "ethernet-phy-ieee802.3-c45";

			};



			slot2_qxgmii1: ethernet-phy@1 {

				reg = <0x1>;

				compatible = "ethernet-phy-ieee802.3-c45";

			};



			slot2_qxgmii2: ethernet-phy@2 {

				reg = <0x2>;

				compatible = "ethernet-phy-ieee802.3-c45";

			};



			slot2_qxgmii3: ethernet-phy@3 {

				reg = <0x3>;

				compatible = "ethernet-phy-ieee802.3-c45";

			};

		};

	};



	fragment@3 {

		target = <&mscc_felix_ports>;



		__overlay__ {

			port@0 {

				status = "okay";

				phy-handle = <&slot2_qxgmii0>;

				phy-mode = "usxgmii";

				managed = "in-band-status";

			};



			port@1 {

				status = "okay";

				phy-handle = <&slot2_qxgmii1>;

				phy-mode = "usxgmii";

				managed = "in-band-status";

			};



			port@2 {

				status = "okay";

				phy-handle = <&slot2_qxgmii2>;

				phy-mode = "usxgmii";

				managed = "in-band-status";

			};



			port@3 {

				status = "okay";

				phy-handle = <&slot2_qxgmii3>;

				phy-mode = "usxgmii";

				managed = "in-band-status";

			};

		};

	};



	fragment@4 {

		target = <&mscc_felix>;



		__overlay__ {

			status = "okay";

		};

	};

};

arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts

0 → 100644
+108 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Device Tree fragment for LS1028A QDS board, serdes 69xx

 *

 * Copyright 2019-2021 NXP

 *

 * Requires a LS1028A QDS board with lane B rework.

 * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2.

 */



/dts-v1/;

/plugin/;



/ {

	fragment@0 {

		target = <&mdio_slot1>;



		__overlay__ {

			#address-cells = <1>;

			#size-cells = <0>;



			slot1_sgmii: ethernet-phy@2 {

				/* AQR112 */

				reg = <0x2>;

				compatible = "ethernet-phy-ieee802.3-c45";

			};

		};

	};



	fragment@1 {

		target = <&enetc_port0>;



		__overlay__ {

			phy-handle = <&slot1_sgmii>;

			phy-mode = "2500base-x";

			managed = "in-band-status";

			status = "okay";

		};

	};



	fragment@2 {

		target = <&mdio_slot2>;



		__overlay__ {

			#address-cells = <1>;

			#size-cells = <0>;



			/* 4 ports on VSC8514 */

			slot2_qsgmii0: ethernet-phy@8 {

				reg = <0x8>;

			};



			slot2_qsgmii1: ethernet-phy@9 {

				reg = <0x9>;

			};



			slot2_qsgmii2: ethernet-phy@a {

				reg = <0xa>;

			};



			slot2_qsgmii3: ethernet-phy@b {

				reg = <0xb>;

			};

		};

	};



	fragment@3 {

		target = <&mscc_felix_ports>;



		__overlay__ {

			port@0 {

				status = "okay";

				phy-handle = <&slot2_qsgmii0>;

				phy-mode = "qsgmii";

				managed = "in-band-status";

			};



			port@1 {

				status = "okay";

				phy-handle = <&slot2_qsgmii1>;

				phy-mode = "qsgmii";

				managed = "in-band-status";

			};



			port@2 {

				status = "okay";

				phy-handle = <&slot2_qsgmii2>;

				phy-mode = "qsgmii";

				managed = "in-band-status";

			};



			port@3 {

				status = "okay";

				phy-handle = <&slot2_qsgmii3>;

				phy-mode = "qsgmii";

				managed = "in-band-status";

			};

		};

	};



	fragment@4 {

		target = <&mscc_felix>;



		__overlay__ {

			status = "okay";

		};

	};

};

arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts

0 → 100644
+82 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Device Tree fragment for LS1028A QDS board, serdes 7777

 *

 * Copyright 2019-2021 NXP

 *

 * Requires a LS1028A QDS board without lane B rework.

 * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing

 * disabled, plugged in slot 1.

 */



/dts-v1/;

/plugin/;



/ {

	fragment@0 {

		target = <&mdio_slot1>;



		__overlay__ {

			#address-cells = <1>;

			#size-cells = <0>;



			/* 4 ports on AQR412 */

			slot1_sxgmii0: ethernet-phy@0 {

				reg = <0x0>;

				compatible = "ethernet-phy-ieee802.3-c45";

			};



			slot1_sxgmii1: ethernet-phy@1 {

				reg = <0x1>;

				compatible = "ethernet-phy-ieee802.3-c45";

			};



			slot1_sxgmii2: ethernet-phy@2 {

				reg = <0x2>;

				compatible = "ethernet-phy-ieee802.3-c45";

			};



			slot1_sxgmii3: ethernet-phy@3 {

				reg = <0x3>;

				compatible = "ethernet-phy-ieee802.3-c45";

			};

		};

	};



	fragment@1 {

		target = <&mscc_felix_ports>;



		__overlay__ {

			port@0 {

				status = "okay";

				phy-handle = <&slot1_sxgmii0>;

				phy-mode = "2500base-x";

			};



			port@1 {

				status = "okay";

				phy-handle = <&slot1_sxgmii1>;

				phy-mode = "2500base-x";

			};



			port@2 {

				status = "okay";

				phy-handle = <&slot1_sxgmii2>;

				phy-mode = "2500base-x";

			};



			port@3 {

				status = "okay";

				phy-handle = <&slot1_sxgmii3>;

				phy-mode = "2500base-x";

			};

		};

	};



	fragment@2 {

		target = <&mscc_felix>;

		__overlay__ {

			status = "okay";

		};

	};

};

arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts

0 → 100644
+107 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Device Tree fragment for LS1028A QDS board, serdes 85bb

 *

 * Copyright 2019-2021 NXP

 *

 * Requires a LS1028A QDS board with lane B rework.

 * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2.

 */



/dts-v1/;

/plugin/;



/ {

	fragment@0 {

		target = <&mdio_slot1>;



		__overlay__ {

			#address-cells = <1>;

			#size-cells = <0>;



			slot1_sgmii: ethernet-phy@1c {

				/* 1st port on VSC8234 */

				reg = <0x1c>;

			};

		};

	};



	fragment@1 {

		target = <&enetc_port0>;



		__overlay__ {

			phy-handle = <&slot1_sgmii>;

			phy-mode = "sgmii";

			managed = "in-band-status";

			status = "okay";

		};

	};



	fragment@2 {

		target = <&mdio_slot2>;



		__overlay__ {

			#address-cells = <1>;

			#size-cells = <0>;



			/* 4 ports on VSC8514 */

			slot2_qsgmii0: ethernet-phy@8 {

				reg = <0x8>;

			};



			slot2_qsgmii1: ethernet-phy@9 {

				reg = <0x9>;

			};



			slot2_qsgmii2: ethernet-phy@a {

				reg = <0xa>;

			};



			slot2_qsgmii3: ethernet-phy@b {

				reg = <0xb>;

			};

		};

	};



	fragment@3 {

		target = <&mscc_felix_ports>;



		__overlay__ {

			port@0 {

				status = "okay";

				phy-handle = <&slot2_qsgmii0>;

				phy-mode = "qsgmii";

				managed = "in-band-status";

			};



			port@1 {

				status = "okay";

				phy-handle = <&slot2_qsgmii1>;

				phy-mode = "qsgmii";

				managed = "in-band-status";

			};



			port@2 {

				status = "okay";

				phy-handle = <&slot2_qsgmii2>;

				phy-mode = "qsgmii";

				managed = "in-band-status";

			};



			port@3 {

				status = "okay";

				phy-handle = <&slot2_qsgmii3>;

				phy-mode = "qsgmii";

				managed = "in-band-status";

			};

		};

	};



	fragment@4 {

		target = <&mscc_felix>;



		__overlay__ {

			status = "okay";

		};

	};

};