Commit 348abd4c authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Clean up cursor registers 



Use REG_BIT() & co. to polish the cursor plane registers.

v2: deal with gvt

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-12-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
parent f6bb74e0

drivers/gpu/drm/i915/display/intel_cursor.c

+12 −13
Original line number Diff line number Diff line
@@ -51,16 +51,16 @@ static u32 intel_cursor_position(const struct intel_plane_state *plane_state) 
	u32 pos = 0;



	if (x < 0) {

		pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;

		pos |= CURSOR_POS_X_SIGN;

		x = -x;

	}

	pos |= x << CURSOR_X_SHIFT;

	pos |= CURSOR_POS_X(x);



	if (y < 0) {

		pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;

		pos |= CURSOR_POS_Y_SIGN;

		y = -y;

	}

	pos |= y << CURSOR_Y_SHIFT;

	pos |= CURSOR_POS_Y(y);



	return pos;

}
@@ -180,7 +180,7 @@ static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) 
	u32 cntl = 0;



	if (crtc_state->gamma_enable)

		cntl |= CURSOR_GAMMA_ENABLE;

		cntl |= CURSOR_PIPE_GAMMA_ENABLE;



	return cntl;

}
@@ -264,7 +264,7 @@ static void i845_cursor_update_arm(struct intel_plane *plane, 
		cntl = plane_state->ctl |

			i845_cursor_ctl_crtc(crtc_state);



		size = (height << 12) | width;

		size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);



		base = intel_cursor_base(plane_state);

		pos = intel_cursor_position(plane_state);
@@ -280,7 +280,7 @@ static void i845_cursor_update_arm(struct intel_plane *plane, 
	    plane->cursor.cntl != cntl) {

		intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);

		intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);

		intel_de_write_fw(dev_priv, CURSIZE, size);

		intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);

		intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);

		intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
@@ -340,13 +340,13 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) 
		return cntl;



	if (crtc_state->gamma_enable)

		cntl = MCURSOR_GAMMA_ENABLE;

		cntl = MCURSOR_PIPE_GAMMA_ENABLE;



	if (crtc_state->csc_enable)

		cntl |= MCURSOR_PIPE_CSC_ENABLE;



	if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))

		cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);

		cntl |= MCURSOR_PIPE_SEL(crtc->pipe);



	return cntl;

}
@@ -502,7 +502,7 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane, 
			i9xx_cursor_ctl_crtc(crtc_state);



		if (width != height)

			fbc_ctl = CUR_FBC_CTL_EN | (height - 1);

			fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);



		base = intel_cursor_base(plane_state);

		pos = intel_cursor_position(plane_state);
@@ -586,13 +586,12 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, 


	val = intel_de_read(dev_priv, CURCNTR(plane->pipe));



	ret = val & MCURSOR_MODE;

	ret = val & MCURSOR_MODE_MASK;



	if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))

		*pipe = plane->pipe;

	else

		*pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>

			MCURSOR_PIPE_SELECT_SHIFT;

		*pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);



	intel_display_power_put(dev_priv, power_domain, wakeref);

drivers/gpu/drm/i915/display/intel_display.c

+2 −2
Original line number Diff line number Diff line
@@ -10004,9 +10004,9 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 
		    intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &

		    DISPLAY_PLANE_ENABLE);

	drm_WARN_ON(&dev_priv->drm,

		    intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);

		    intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);

	drm_WARN_ON(&dev_priv->drm,

		    intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);

		    intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);



	intel_de_write(dev_priv, PIPECONF(pipe), 0);

	intel_de_posting_read(dev_priv, PIPECONF(pipe));

drivers/gpu/drm/i915/gvt/display.c

+2 −2
Original line number Diff line number Diff line
@@ -187,7 +187,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
				~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);

			vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;

			vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;

			vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;

			vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;

			vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;

		}
@@ -498,7 +498,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
	for_each_pipe(dev_priv, pipe) {

		vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;

		vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;

		vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;

		vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;

		vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;

	}

drivers/gpu/drm/i915/gvt/fb_decoder.c

+1 −1
Original line number Diff line number Diff line
@@ -342,7 +342,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, 
		return -ENODEV;



	val = vgpu_vreg_t(vgpu, CURCNTR(pipe));

	mode = val & MCURSOR_MODE;

	mode = val & MCURSOR_MODE_MASK;

	plane->enabled = (mode != MCURSOR_MODE_DISABLE);

	if (!plane->enabled)

		return -ENODEV;

drivers/gpu/drm/i915/i915_reg.h

+39 −32
Original line number Diff line number Diff line
@@ -5756,44 +5756,50 @@ enum { 
/* Cursor A & B regs */

#define _CURACNTR		0x70080

/* Old style CUR*CNTR flags (desktop 8xx) */

#define   CURSOR_ENABLE		0x80000000

#define   CURSOR_GAMMA_ENABLE	0x40000000

#define   CURSOR_STRIDE_SHIFT	28

#define   CURSOR_STRIDE(x)	((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */

#define   CURSOR_FORMAT_SHIFT	24

#define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)

#define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)

#define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)

#define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)

#define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)

#define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)

#define   CURSOR_ENABLE			REG_BIT(31)

#define   CURSOR_PIPE_GAMMA_ENABLE	REG_BIT(30)

#define   CURSOR_STRIDE_MASK	REG_GENMASK(29, 28)

#define   CURSOR_STRIDE(stride)	REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */

#define   CURSOR_FORMAT_MASK	REG_GENMASK(26, 24)

#define   CURSOR_FORMAT_2C	REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)

#define   CURSOR_FORMAT_3C	REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)

#define   CURSOR_FORMAT_4C	REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)

#define   CURSOR_FORMAT_ARGB	REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)

#define   CURSOR_FORMAT_XRGB	REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)

/* New style CUR*CNTR flags */

#define   MCURSOR_MODE		0x27

#define   MCURSOR_ARB_SLOTS_MASK	REG_GENMASK(30, 28) /* icl+ */

#define   MCURSOR_ARB_SLOTS(x)		REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */

#define   MCURSOR_PIPE_SEL_MASK		REG_GENMASK(29, 28)

#define   MCURSOR_PIPE_SEL(pipe)	REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))

#define   MCURSOR_PIPE_GAMMA_ENABLE	REG_BIT(26)

#define   MCURSOR_PIPE_CSC_ENABLE	REG_BIT(24) /* ilk+ */

#define   MCURSOR_ROTATE_180		REG_BIT(15)

#define   MCURSOR_TRICKLE_FEED_DISABLE	REG_BIT(14)

#define   MCURSOR_MODE_MASK		0x27

#define   MCURSOR_MODE_DISABLE		0x00

#define   MCURSOR_MODE_128_32B_AX	0x02

#define   MCURSOR_MODE_256_32B_AX	0x03

#define   MCURSOR_MODE_64_32B_AX	0x07

#define   MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)

#define   MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)

#define   MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)

#define   MCURSOR_ARB_SLOTS_MASK	REG_GENMASK(30, 28) /* icl+ */

#define   MCURSOR_ARB_SLOTS(x)		REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */

#define   MCURSOR_PIPE_SELECT_MASK	(0x3 << 28)

#define   MCURSOR_PIPE_SELECT_SHIFT	28

#define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)

#define   MCURSOR_GAMMA_ENABLE  (1 << 26)

#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */

#define   MCURSOR_ROTATE_180	(1 << 15)

#define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)

#define   MCURSOR_MODE_128_ARGB_AX	(0x20 | MCURSOR_MODE_128_32B_AX)

#define   MCURSOR_MODE_256_ARGB_AX	(0x20 | MCURSOR_MODE_256_32B_AX)

#define   MCURSOR_MODE_64_ARGB_AX	(0x20 | MCURSOR_MODE_64_32B_AX)

#define _CURABASE		0x70084

#define _CURAPOS		0x70088

#define   CURSOR_POS_MASK       0x007FF

#define   CURSOR_POS_SIGN       0x8000

#define   CURSOR_X_SHIFT        0

#define   CURSOR_Y_SHIFT        16

#define CURSIZE			_MMIO(0x700a0) /* 845/865 */

#define   CURSOR_POS_Y_SIGN		REG_BIT(31)

#define   CURSOR_POS_Y_MASK		REG_GENMASK(30, 16)

#define   CURSOR_POS_Y(y)		REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))

#define   CURSOR_POS_X_SIGN		REG_BIT(15)

#define   CURSOR_POS_X_MASK		REG_GENMASK(14, 0)

#define   CURSOR_POS_X(x)		REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))

#define _CURASIZE		0x700a0 /* 845/865 */

#define   CURSOR_HEIGHT_MASK		REG_GENMASK(21, 12)

#define   CURSOR_HEIGHT(h)		REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))

#define   CURSOR_WIDTH_MASK		REG_GENMASK(9, 0)

#define   CURSOR_WIDTH(w)		REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))

#define _CUR_FBC_CTL_A		0x700a0 /* ivb+ */

#define   CUR_FBC_CTL_EN	(1 << 31)

#define   CUR_FBC_EN			REG_BIT(31)

#define   CUR_FBC_HEIGHT_MASK		REG_GENMASK(7, 0)

#define   CUR_FBC_HEIGHT(h)		REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))

#define _CURASURFLIVE		0x700ac /* g4x+ */

#define _CURBCNTR		0x700c0

#define _CURBBASE		0x700c4
@@ -5806,6 +5812,7 @@ enum { 
#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)

#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)

#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)

#define CURSIZE(pipe) _CURSOR2(pipe, _CURASIZE)

#define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)

#define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)