Commit 356e2385 authored by Eilon Greenstein's avatar Eilon Greenstein Committed by David S. Miller
Browse files

bnx2x: Clean-up 



Whitespaces, empty lines, 80 columns, indentations and removing redundant
parenthesis

Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent f5372251

drivers/net/bnx2x.h

+1 −1
Original line number Diff line number Diff line
@@ -906,7 +906,7 @@ struct bnx2x { 
	u32			lin_cnt;



	int			state;

#define BNX2X_STATE_CLOSED		0x0

#define BNX2X_STATE_CLOSED		0

#define BNX2X_STATE_OPENING_WAIT4_LOAD	0x1000

#define BNX2X_STATE_OPENING_WAIT4_PORT	0x2000

#define BNX2X_STATE_OPEN		0x3000

drivers/net/bnx2x_fw_defs.h

+25 −29
Original line number Diff line number Diff line
@@ -217,14 +217,13 @@ 
#define X_ETH_LOCAL_RING_SIZE 13

#define FIRST_BD_IN_PKT 0

#define PARSE_BD_INDEX 1

#define NUM_OF_ETH_BDS_IN_PAGE \

	((PAGE_SIZE) / (STRUCT_SIZE(eth_tx_bd)/8))

#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))





/* Rx ring params */

#define U_ETH_LOCAL_BD_RING_SIZE (16)

#define U_ETH_LOCAL_SGE_RING_SIZE (12)

#define U_ETH_SGL_SIZE (8)

#define U_ETH_LOCAL_BD_RING_SIZE 16

#define U_ETH_LOCAL_SGE_RING_SIZE 12

#define U_ETH_SGL_SIZE 8





#define U_ETH_BDS_PER_PAGE_MASK \
@@ -246,15 +245,15 @@ 
#define U_ETH_UNDEFINED_Q 0xFF



/* values of command IDs in the ramrod message */

#define RAMROD_CMD_ID_ETH_PORT_SETUP (80)

#define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)

#define RAMROD_CMD_ID_ETH_STAT_QUERY (90)

#define RAMROD_CMD_ID_ETH_UPDATE (100)

#define RAMROD_CMD_ID_ETH_HALT (105)

#define RAMROD_CMD_ID_ETH_SET_MAC (110)

#define RAMROD_CMD_ID_ETH_CFC_DEL (115)

#define RAMROD_CMD_ID_ETH_PORT_DEL (120)

#define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)

#define RAMROD_CMD_ID_ETH_PORT_SETUP 80

#define RAMROD_CMD_ID_ETH_CLIENT_SETUP 85

#define RAMROD_CMD_ID_ETH_STAT_QUERY 90

#define RAMROD_CMD_ID_ETH_UPDATE 100

#define RAMROD_CMD_ID_ETH_HALT 105

#define RAMROD_CMD_ID_ETH_SET_MAC 110

#define RAMROD_CMD_ID_ETH_CFC_DEL 115

#define RAMROD_CMD_ID_ETH_PORT_DEL 120

#define RAMROD_CMD_ID_ETH_FORWARD_SETUP 125





/* command values for set mac command */
@@ -271,8 +270,8 @@ 
#define ETH_MAX_RX_CLIENTS_E1H 25



/* Maximal aggregation queues supported */

#define ETH_MAX_AGGREGATION_QUEUES_E1 (32)

#define ETH_MAX_AGGREGATION_QUEUES_E1H (64)

#define ETH_MAX_AGGREGATION_QUEUES_E1 32

#define ETH_MAX_AGGREGATION_QUEUES_E1H 64



/* ETH RSS modes */

#define ETH_RSS_MODE_DISABLED 0
@@ -301,7 +300,7 @@ 
#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)



/* microcode fixed page page size 4K (chains and ring segments) */

#define MC_PAGE_SIZE (4096)

#define MC_PAGE_SIZE 4096





/* Host coalescing constants */
@@ -348,16 +347,16 @@ 
#define ATTENTION_ID 4



/* max number of slow path commands per port */

#define MAX_RAMRODS_PER_PORT (8)

#define MAX_RAMRODS_PER_PORT 8



/* values for RX ETH CQE type field */

#define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)

#define RX_ETH_CQE_TYPE_ETH_RAMROD (1)

#define RX_ETH_CQE_TYPE_ETH_FASTPATH 0

#define RX_ETH_CQE_TYPE_ETH_RAMROD 1





/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/

#define EMULATION_FREQUENCY_FACTOR (1600)

#define FPGA_FREQUENCY_FACTOR (100)

#define EMULATION_FREQUENCY_FACTOR 1600

#define FPGA_FREQUENCY_FACTOR 100



#define TIMERS_TICK_SIZE_CHIP (1e-3)

#define TIMERS_TICK_SIZE_EMUL \
@@ -371,12 +370,9 @@ 
#define TSEMI_CLK1_RESUL_FPGA \

 ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))



#define USEMI_CLK1_RESUL_CHIP \

 (TIMERS_TICK_SIZE_CHIP)

#define USEMI_CLK1_RESUL_EMUL \

 (TIMERS_TICK_SIZE_EMUL)

#define USEMI_CLK1_RESUL_FPGA \

 (TIMERS_TICK_SIZE_FPGA)

#define USEMI_CLK1_RESUL_CHIP (TIMERS_TICK_SIZE_CHIP)

#define USEMI_CLK1_RESUL_EMUL (TIMERS_TICK_SIZE_EMUL)

#define USEMI_CLK1_RESUL_FPGA (TIMERS_TICK_SIZE_FPGA)



#define XSEMI_CLK1_RESUL_CHIP (1e-3)

#define XSEMI_CLK1_RESUL_EMUL \
@@ -401,7 +397,7 @@ 
#define XSTORM_IP_ID_ROLL_HALF 0x8000

#define XSTORM_IP_ID_ROLL_ALL 0



#define FW_LOG_LIST_SIZE (50)

#define FW_LOG_LIST_SIZE 50



#define NUM_OF_PROTOCOLS 4

#define NUM_OF_SAFC_BITS 16

drivers/net/bnx2x_hsi.h

+0 −4
Original line number Diff line number Diff line
@@ -806,11 +806,7 @@ struct mf_cfg { 


	struct shared_mf_cfg	shared_mf_config;

	struct port_mf_cfg	port_mf_config[PORT_MAX];

#if defined(b710)

	struct func_mf_cfg	func_mf_config[E1_FUNC_MAX];

#else

	struct func_mf_cfg	func_mf_config[E1H_FUNC_MAX];

#endif



};

drivers/net/bnx2x_link.c

+2 −5
Original line number Diff line number Diff line
@@ -1923,9 +1923,6 @@ static void bnx2x_ext_phy_reset(struct link_params *params, 
			break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:

			{

			u16 emac_base;

			emac_base = (params->port) ? GRCBASE_EMAC0 :

					GRCBASE_EMAC1;



			/* Restore normal power mode*/

			bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,

drivers/net/bnx2x_link.h

+1 −2
Original line number Diff line number Diff line
@@ -66,8 +66,6 @@ struct link_params { 
	/* Device parameters */

	u8 mac_addr[6];







	/* shmem parameters */

	u32 shmem_base;

	u32 speed_cap_mask;
@@ -182,4 +180,5 @@ u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars); 
/* One-time initialization for external phy after power up */

u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base);





#endif /* BNX2X_LINK_H */