Commit 36ada250 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2021-01-22' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Regular fixes pull, nothing too major in here, just some core fixes,
  one vc4, bunch of i915 and a bunch of amdgpu.

  core:
   - atomic: Release state on error
   - syncobj: Fix use-after-free
   - ttm: Don't use GFP_TRANSHUGE_LIGTH
   - vram-helper: Fix memory leak in vmap

  vc4:
   - Unify driver naming for PCM

  i915:
   - HDCP fixes
   - PMU wakeref fix
   - Fix HWSP validity race
   - Fix DP protocol converter accidental 4:4:4->4:2:0 conversion for RGB

  amdgpu:
   - Green Sardine fixes
   - Vangogh fixes
   - Renoir fixes
   - Misc display fixes"

* tag 'drm-fixes-2021-01-22' of git://anongit.freedesktop.org/drm/drm: (21 commits)
  drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3
  drm/amdgpu: modify GCR_GENERAL_CNTL for Vangogh
  drm/amdgpu/pm: no need GPU status set since mmnbif_gpu_BIF_DOORBELL_FENCE_CNTL added in FSDL
  drm/amd/display: Fixed corruptions on HPDRX link loss restore
  drm/amd/display: Use hardware sequencer functions for PG control
  drm/amd/display: Change function decide_dp_link_settings to avoid infinite looping
  drm/amd/display: Allow PSTATE chnage when no displays are enabled
  drm/amd/display: Update dram_clock_change_latency for DCN2.1
  drm/amdgpu: remove gpu info firmware of green sardine
  drm/amd/display: DCN2X Find Secondary Pipe properly in MPO + ODM Case
  drm/syncobj: Fix use-after-free
  drm/vram-helper: Reuse existing page mappings in vmap
  drm/atomic: put state on error path
  drm/i915: Only enable DFP 4:4:4->4:2:0 conversion when outputting YCbCr 4:4:4
  drm/i915: Check for rq->hwsp validity after acquiring RCU lock
  drm/i915/pmu: Don't grab wakeref when enabling events
  drm/i915/gt: Prevent use of engine->wa_ctx after error
  drm/vc4: Unify PCM card's driver_name
  drm/ttm: stop using GFP_TRANSHUGE_LIGHT
  drm/i915/hdcp: Get conn while content_type changed
  ...
parents 9f29bd8b 06ee38dc

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+0 −1
Original line number Diff line number Diff line
@@ -81,7 +81,6 @@ MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin"); 
MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");

MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");

MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin");

MODULE_FIRMWARE("amdgpu/green_sardine_gpu_info.bin");



#define AMDGPU_RESUME_MS		2000

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+3 −1
Original line number Diff line number Diff line
@@ -119,6 +119,8 @@ 
#define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1

#define mmSPI_CONFIG_CNTL_Vangogh                0x2440

#define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1

#define mmGCR_GENERAL_CNTL_Vangogh               0x1580

#define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0



#define mmCP_HYP_PFP_UCODE_ADDR			0x5814

#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX	1
@@ -3244,7 +3246,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

+61 −23
Original line number Diff line number Diff line
@@ -491,12 +491,11 @@ mmhub_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 
{

	uint32_t def, data, def1, data1;



	def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);

	def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL);

	def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);



	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {

		data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;



		data &= ~MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK;

		data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |

		           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |

		           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
@@ -505,8 +504,7 @@ mmhub_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 
		           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);



	} else {

		data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;



		data |= MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK;

		data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |

			  DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |

			  DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
@@ -516,7 +514,7 @@ mmhub_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 
	}



	if (def != data)

		WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);

		WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL, data);

	if (def1 != data1)

		WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);

}
@@ -525,17 +523,44 @@ static void 
mmhub_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev,

					   bool enable)

{

	uint32_t def, data;



	def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);



	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))

		data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;

	else

		data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;

	uint32_t def, data, def1, data1, def2, data2;



	def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL);

	def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL);

	def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL);



	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {

		data &= ~MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK;

		data1 &= !(DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |

			DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |

			DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |

			DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |

			DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);

		data2 &= !(DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |

			DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |

			DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |

			DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |

			DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);

	} else {

		data |= MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK;

		data1 |= (DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |

			DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |

			DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |

			DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |

			DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);

		data2 |= (DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |

			DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |

			DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |

			DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |

			DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);

	}



	if (def != data)

		WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);

		WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL, data);

	if (def1 != data1)

		WREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL, data1);

	if (def2 != data2)

		WREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL, data2);

}



static int mmhub_v2_3_set_clockgating(struct amdgpu_device *adev,
@@ -554,26 +579,39 @@ static int mmhub_v2_3_set_clockgating(struct amdgpu_device *adev, 


static void mmhub_v2_3_get_clockgating(struct amdgpu_device *adev, u32 *flags)

{

	int data, data1;

	int data, data1, data2, data3;



	if (amdgpu_sriov_vf(adev))

		*flags = 0;



	data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);

	data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

	data = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

	data1  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL);

	data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL);

	data3 = RREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL);



	/* AMD_CG_SUPPORT_MC_MGCG */

	if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&

	    !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |

	if (!(data & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |

		       DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |

		       DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |

		       DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |

		       DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |

		       DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))

		       DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))

		&& !(data1 & MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK)) {

			*flags |= AMD_CG_SUPPORT_MC_MGCG;

	}



	/* AMD_CG_SUPPORT_MC_LS */

	if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)

	if (!(data1 & MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK)

		&& !(data2 & (DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |

				DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |

				DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |

				DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |

				DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK))

		&& !(data3 & (DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |

				DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |

				DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |

				DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |

				DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK)))

		*flags |= AMD_CG_SUPPORT_MC_LS;

}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

+4 −2
Original line number Diff line number Diff line
@@ -251,6 +251,7 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, 
	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

	bool force_reset = false;

	bool update_uclk = false;

	bool p_state_change_support;



	if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present)

		return;
@@ -291,8 +292,9 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, 
		clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;



	clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;

	if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {

		clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;

	p_state_change_support = new_clocks->p_state_change_support || (display_count == 0);

	if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {

		clk_mgr_base->clks.p_state_change_support = p_state_change_support;



		/* to disable P-State switching, set UCLK min = max */

		if (!clk_mgr_base->clks.p_state_change_support)

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+5 −2
Original line number Diff line number Diff line
@@ -2399,6 +2399,9 @@ static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_setting 
			initial_link_setting;

	uint32_t link_bw;



	if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))

		return false;



	/* search for the minimum link setting that:

	 * 1. is supported according to the link training result

	 * 2. could support the b/w requested by the timing
@@ -3045,14 +3048,14 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd 
		for (i = 0; i < MAX_PIPES; i++) {

			pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];

			if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&

					pipe_ctx->stream->link == link)

					pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)

				core_link_disable_stream(pipe_ctx);

		}



		for (i = 0; i < MAX_PIPES; i++) {

			pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];

			if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&

					pipe_ctx->stream->link == link)

					pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)

				core_link_enable_stream(link->dc->current_state, pipe_ctx);

		}