Commit 36f91e63 authored by Kathiravan T's avatar Kathiravan T Committed by Bjorn Andersson
Browse files

arm64: dts: ipq6018: enable DVFS support 



Add A53 PLL, APCS clock, RPM Glink, RPM message RAM, cpu-opp-table,
SMPA2 regulator to enable the cpu frequency on IPQ6018.

Co-developed-by: default avatarSivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: default avatarSivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: default avatarKathiravan T <kathirav@codeaurora.org>
Link: https://lore.kernel.org/r/1597648720-13649-3-git-send-email-kathirav@codeaurora.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 5a8c1669

arch/arm64/boot/dts/qcom/ipq6018.dtsi

+93 −3
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,gcc-ipq6018.h>

#include <dt-bindings/reset/qcom,gcc-ipq6018.h>

#include <dt-bindings/clock/qcom,apss-ipq.h>



/ {

	#address-cells = <2>;
@@ -38,6 +39,10 @@ CPU0: cpu@0 { 
			reg = <0x0>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;

			clock-names = "cpu";

			operating-points-v2 = <&cpu_opp_table>;

			cpu-supply = <&ipq6018_s2>;

		};



		CPU1: cpu@1 {
@@ -46,6 +51,10 @@ CPU1: cpu@1 { 
			enable-method = "psci";

			reg = <0x1>;

			next-level-cache = <&L2_0>;

			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;

			clock-names = "cpu";

			operating-points-v2 = <&cpu_opp_table>;

			cpu-supply = <&ipq6018_s2>;

		};



		CPU2: cpu@2 {
@@ -54,6 +63,10 @@ CPU2: cpu@2 { 
			enable-method = "psci";

			reg = <0x2>;

			next-level-cache = <&L2_0>;

			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;

			clock-names = "cpu";

			operating-points-v2 = <&cpu_opp_table>;

			cpu-supply = <&ipq6018_s2>;

		};



		CPU3: cpu@3 {
@@ -62,6 +75,10 @@ CPU3: cpu@3 { 
			enable-method = "psci";

			reg = <0x3>;

			next-level-cache = <&L2_0>;

			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;

			clock-names = "cpu";

			operating-points-v2 = <&cpu_opp_table>;

			cpu-supply = <&ipq6018_s2>;

		};



		L2_0: l2-cache {
@@ -70,6 +87,42 @@ L2_0: l2-cache { 
		};

	};



	cpu_opp_table: cpu_opp_table {

		compatible = "operating-points-v2";

		opp-shared;



		opp-864000000 {

			opp-hz = /bits/ 64 <864000000>;

			opp-microvolt = <725000>;

			clock-latency-ns = <200000>;

		};

		opp-1056000000 {

			opp-hz = /bits/ 64 <1056000000>;

			opp-microvolt = <787500>;

			clock-latency-ns = <200000>;

		};

		opp-1320000000 {

			opp-hz = /bits/ 64 <1320000000>;

			opp-microvolt = <862500>;

			clock-latency-ns = <200000>;

		};

		opp-1440000000 {

			opp-hz = /bits/ 64 <1440000000>;

			opp-microvolt = <925000>;

			clock-latency-ns = <200000>;

		};

		opp-1608000000 {

			opp-hz = /bits/ 64 <1608000000>;

			opp-microvolt = <987500>;

			clock-latency-ns = <200000>;

		};

		opp-1800000000 {

			opp-hz = /bits/ 64 <1800000000>;

			opp-microvolt = <1062500>;

			clock-latency-ns = <200000>;

		};

	};



	firmware {

		scm {

			compatible = "qcom,scm";
@@ -98,6 +151,11 @@ reserved-memory { 
		#size-cells = <2>;

		ranges;



		rpm_msg_ram: memory@0x60000 {

			reg = <0x0 0x60000 0x0 0x6000>;

			no-map;

		};



		tz: tz@48500000 {

			reg = <0x0 0x48500000 0x0 0x00200000>;

			no-map;
@@ -294,12 +352,22 @@ watchdog@b017000 { 
		};



		apcs_glb: mailbox@b111000 {

			compatible = "qcom,ipq8074-apcs-apps-global";

			reg = <0x0b111000 0xc>;



			compatible = "qcom,ipq6018-apcs-apps-global";

			reg = <0x0b111000 0x1000>;

			#clock-cells = <1>;

			clocks = <&a53pll>, <&xo>;

			clock-names = "pll", "xo";

			#mbox-cells = <1>;

		};



		a53pll: clock@b116000 {

			compatible = "qcom,ipq6018-a53pll";

			reg = <0x0b116000 0x40>;

			#clock-cells = <0>;

			clocks = <&xo>;

			clock-names = "xo";

		};



		timer {

			compatible = "arm,armv8-timer";

			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -440,4 +508,26 @@ wcss_smp2p_in: slave-kernel { 
			#interrupt-cells = <2>;

		};

	};



	rpm-glink {

		compatible = "qcom,glink-rpm";

		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;

		qcom,rpm-msg-ram = <&rpm_msg_ram>;

		mboxes = <&apcs_glb 0>;



		rpm_requests: glink-channel {

			compatible = "qcom,rpm-ipq6018";

			qcom,glink-channels = "rpm_requests";



			regulators {

				compatible = "qcom,rpm-mp5496-regulators";



				ipq6018_s2: s2 {

					regulator-min-microvolt = <725000>;

					regulator-max-microvolt = <1062500>;

					regulator-always-on;

				};

			};

		};

	};

};