Commit 376002f4 authored by Bokun Zhang's avatar Bokun Zhang Committed by Alex Deucher
Browse files

drm/amd/amdgpu: Use IP discovery data to determine VCN enablement instead of MMSCH 



In the past, we use MMSCH to determine whether a VCN is enabled or not.
This is not reliable since after a FLR, MMSCH may report junk data.

It is better to use IP discovery data.

Signed-off-by: default avatarBokun Zhang <Bokun.Zhang@amd.com>
Signed-off-by: default avatarPeng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 942ab769

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+8 −0
Original line number Diff line number Diff line
@@ -373,6 +373,14 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int n 
	return -EINVAL;

}





int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int vcn_instance,

				     int *major, int *minor, int *revision)

{

	return amdgpu_discovery_get_ip_version(adev, VCN_HWID,

					       vcn_instance, major, minor, revision);

}



void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)

{

	struct binary_header *bhdr;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h

+3 −0
Original line number Diff line number Diff line
@@ -32,6 +32,9 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev); 
void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev);

int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,

                                    int *major, int *minor, int *revision);



int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int vcn_instance,

				     int *major, int *minor, int *revision);

int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);



#endif /* __AMDGPU_DISCOVERY__ */

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

+23 −0
Original line number Diff line number Diff line
@@ -288,6 +288,29 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 
	return 0;

}



bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)

{

	bool ret = false;



	int major;

	int minor;

	int revision;



	/* if cannot find IP data, then this VCN does not exist */

	if (amdgpu_discovery_get_vcn_version(adev, vcn_instance, &major, &minor, &revision) != 0)

		return true;



	if ((type == VCN_ENCODE_RING) && (revision & VCN_BLOCK_ENCODE_DISABLE_MASK)) {

		ret = true;

	} else if ((type == VCN_DECODE_RING) && (revision & VCN_BLOCK_DECODE_DISABLE_MASK)) {

		ret = true;

	} else if ((type == VCN_UNIFIED_RING) && (revision & VCN_BLOCK_QUEUE_DISABLE_MASK)) {

		ret = true;

	}



	return ret;

}



int amdgpu_vcn_suspend(struct amdgpu_device *adev)

{

	unsigned size;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+13 −0
Original line number Diff line number Diff line
@@ -280,6 +280,16 @@ struct amdgpu_vcn_decode_buffer { 
	uint32_t pad[30];

};



#define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80

#define VCN_BLOCK_DECODE_DISABLE_MASK 0x40

#define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0



enum vcn_ring_type {

	VCN_ENCODE_RING,

	VCN_DECODE_RING,

	VCN_UNIFIED_RING,

};



int amdgpu_vcn_sw_init(struct amdgpu_device *adev);

int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);

int amdgpu_vcn_suspend(struct amdgpu_device *adev);
@@ -287,6 +297,9 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev); 
void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);

void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);



bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev,

				enum vcn_ring_type type, uint32_t vcn_instance);



int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);

int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);

int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

+14 −39
Original line number Diff line number Diff line
@@ -87,16 +87,18 @@ static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 
static int vcn_v3_0_early_init(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int i;



	if (amdgpu_sriov_vf(adev)) {

		adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;

		for (i = 0; i < VCN_INSTANCES_SIENNA_CICHLID; i++)

			if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i))

				adev->vcn.num_vcn_inst++;

		adev->vcn.harvest_config = 0;

		adev->vcn.num_enc_rings = 1;



	} else {

		if (adev->asic_type == CHIP_SIENNA_CICHLID) {

			u32 harvest;

			int i;



			adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;

			for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
@@ -151,7 +153,8 @@ static int vcn_v3_0_sw_init(void *handle) 
		adev->firmware.fw_size +=

			ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);



		if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) {

		if ((adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) ||

		    (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)) {

			adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;

			adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;

			adev->firmware.fw_size +=
@@ -325,19 +328,17 @@ static int vcn_v3_0_hw_init(void *handle) 
				continue;



			ring = &adev->vcn.inst[i].ring_dec;

			if (ring->sched.ready) {

			ring->wptr = 0;

			ring->wptr_old = 0;

			vcn_v3_0_dec_ring_set_wptr(ring);

			}

			ring->sched.ready = true;



			for (j = 0; j < adev->vcn.num_enc_rings; ++j) {

				ring = &adev->vcn.inst[i].ring_enc[j];

				if (ring->sched.ready) {

				ring->wptr = 0;

				ring->wptr_old = 0;

				vcn_v3_0_enc_ring_set_wptr(ring);

				}

				ring->sched.ready = true;

			}

		}

	} else {
@@ -1304,8 +1305,6 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 
	uint32_t table_size;

	uint32_t size, size_dw;



	bool is_vcn_ready;



	struct mmsch_v3_0_cmd_direct_write

		direct_wt = { {0} };

	struct mmsch_v3_0_cmd_direct_read_modify_write
@@ -1497,30 +1496,6 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 
		}

	}



	/* 6, check each VCN's init_status

	 * if it remains as 0, then this VCN is not assigned to current VF

	 * do not start ring for this VCN

	 */

	size = sizeof(struct mmsch_v3_0_init_header);

	table_loc = (uint32_t *)table->cpu_addr;

	memcpy(&header, (void *)table_loc, size);



	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {

		if (adev->vcn.harvest_config & (1 << i))

			continue;



		is_vcn_ready = (header.inst[i].init_status == 1);

		if (!is_vcn_ready)

			DRM_INFO("VCN(%d) engine is disabled by hypervisor\n", i);



		ring = &adev->vcn.inst[i].ring_dec;

		ring->sched.ready = is_vcn_ready;

		for (j = 0; j < adev->vcn.num_enc_rings; ++j) {

			ring = &adev->vcn.inst[i].ring_enc[j];

			ring->sched.ready = is_vcn_ready;

		}

	}



	return 0;

}