Commit 386ea27c authored by Le Ma's avatar Le Ma Committed by Alex Deucher
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drm/amdgpu: adjust some basic elements for multiple AID case 



add some elements below:
 - num_aid
 - aid_id for each sdma instance
 - num_inst_per_aid for sdma

and extend macro size below:
 - SDMA_MAX_INSTANCES to 16
 - AMDGPU_MAX_RINGS to 96
 - AMDGPU_MAX_HWIP_RINGS to 32

v2: move aid_id from amdgpu_ring to amdgpu_sdma_instance. (Lijo)

Signed-off-by: default avatarLe Ma <le.ma@amd.com>
Acked-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0ee20b86

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -1051,6 +1051,7 @@ struct amdgpu_device { 




	bool                            job_hang;

	bool                            job_hang;

	bool                            dc_enabled;

	bool                            dc_enabled;

	uint32_t			num_aid;

};

};





static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)

static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

+2 −2
Original line number Original line Diff line number Diff line
@@ -37,8 +37,8 @@ struct amdgpu_job; 
struct amdgpu_vm;

struct amdgpu_vm;





/* max number of rings */

/* max number of rings */

#define AMDGPU_MAX_RINGS		28

#define AMDGPU_MAX_RINGS		96

#define AMDGPU_MAX_HWIP_RINGS		8

#define AMDGPU_MAX_HWIP_RINGS		32

#define AMDGPU_MAX_GFX_RINGS		2

#define AMDGPU_MAX_GFX_RINGS		2

#define AMDGPU_MAX_SW_GFX_RINGS         2

#define AMDGPU_MAX_SW_GFX_RINGS         2

#define AMDGPU_MAX_COMPUTE_RINGS	8

#define AMDGPU_MAX_COMPUTE_RINGS	8

drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h

+3 −1
Original line number Original line Diff line number Diff line
@@ -26,7 +26,7 @@ 
#include "amdgpu_ras.h"

#include "amdgpu_ras.h"





/* max number of IP instances */

/* max number of IP instances */

#define AMDGPU_MAX_SDMA_INSTANCES		8

#define AMDGPU_MAX_SDMA_INSTANCES		16





enum amdgpu_sdma_irq {

enum amdgpu_sdma_irq {

	AMDGPU_SDMA_IRQ_INSTANCE0  = 0,

	AMDGPU_SDMA_IRQ_INSTANCE0  = 0,
@@ -49,6 +49,7 @@ struct amdgpu_sdma_instance { 
	struct amdgpu_ring	ring;

	struct amdgpu_ring	ring;

	struct amdgpu_ring	page;

	struct amdgpu_ring	page;

	bool			burst_nop;

	bool			burst_nop;

	uint32_t		aid_id;

};

};





struct amdgpu_sdma_ras {

struct amdgpu_sdma_ras {
@@ -66,6 +67,7 @@ struct amdgpu_sdma { 
	struct amdgpu_irq_src	srbm_write_irq;

	struct amdgpu_irq_src	srbm_write_irq;





	int			num_instances;

	int			num_instances;

	int			num_inst_per_aid;

	uint32_t                    srbm_soft_reset;

	uint32_t                    srbm_soft_reset;

	bool			has_page_queue;

	bool			has_page_queue;

	struct ras_common_if	*ras_if;

	struct ras_common_if	*ras_if;