Commit 38bb46f9 authored by WANG Xuerui's avatar WANG Xuerui Committed by Huacai Chen
Browse files

LoongArch: Prepare for assemblers with proper FCSR class support 



The GNU assembler (as of 2.40) mis-treats FCSR operands as GPRs, but
the LLVM IAS does not. Probe for this and refer to FCSRs as "$fcsrNN"
if support is present.

Signed-off-by: default avatarWANG Xuerui <git@xen0n.name>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent 24da0249

arch/loongarch/Kconfig

+3 −0
Original line number Original line Diff line number Diff line
@@ -241,6 +241,9 @@ config SCHED_OMIT_FRAME_POINTER 
config AS_HAS_EXPLICIT_RELOCS

config AS_HAS_EXPLICIT_RELOCS

	def_bool $(as-instr,x:pcalau12i \$t0$(comma)%pc_hi20(x))

	def_bool $(as-instr,x:pcalau12i \$t0$(comma)%pc_hi20(x))





config AS_HAS_FCSR_CLASS

	def_bool $(as-instr,movfcsr2gr \$t0$(comma)\$fcsr0)



menu "Kernel type and options"

menu "Kernel type and options"





source "kernel/Kconfig.hz"

source "kernel/Kconfig.hz"

arch/loongarch/include/asm/fpregdef.h

+7 −0
Original line number Original line Diff line number Diff line
@@ -40,6 +40,7 @@ 
#define fs6	$f30

#define fs6	$f30

#define fs7	$f31

#define fs7	$f31





#ifndef CONFIG_AS_HAS_FCSR_CLASS

/*

/*

 * Current binutils expects *GPRs* at FCSR position for the FCSR

 * Current binutils expects *GPRs* at FCSR position for the FCSR

 * operation instructions, so define aliases for those used.

 * operation instructions, so define aliases for those used.
@@ -48,5 +49,11 @@ 
#define fcsr1	$r1

#define fcsr1	$r1

#define fcsr2	$r2

#define fcsr2	$r2

#define fcsr3	$r3

#define fcsr3	$r3

#else

#define fcsr0	$fcsr0

#define fcsr1	$fcsr1

#define fcsr2	$fcsr2

#define fcsr3	$fcsr3

#endif





#endif /* _ASM_FPREGDEF_H */
 
#endif /* _ASM_FPREGDEF_H */

arch/loongarch/include/asm/loongarch.h

+8 −1
Original line number Original line Diff line number Diff line
@@ -1441,11 +1441,18 @@ __BUILD_CSR_OP(tlbidx) 
#define EXCCODE_INT_START	64

#define EXCCODE_INT_START	64

#define EXCCODE_INT_END		(EXCCODE_INT_START + EXCCODE_INT_NUM - 1)

#define EXCCODE_INT_END		(EXCCODE_INT_START + EXCCODE_INT_NUM - 1)





/* FPU register names */

/* FPU Status Register Names */

#ifndef CONFIG_AS_HAS_FCSR_CLASS

#define LOONGARCH_FCSR0	$r0

#define LOONGARCH_FCSR0	$r0

#define LOONGARCH_FCSR1	$r1

#define LOONGARCH_FCSR1	$r1

#define LOONGARCH_FCSR2	$r2

#define LOONGARCH_FCSR2	$r2

#define LOONGARCH_FCSR3	$r3

#define LOONGARCH_FCSR3	$r3

#else

#define LOONGARCH_FCSR0	$fcsr0

#define LOONGARCH_FCSR1	$fcsr1

#define LOONGARCH_FCSR2	$fcsr2

#define LOONGARCH_FCSR3	$fcsr3

#endif





/* FPU Status Register Values */

/* FPU Status Register Values */

#define FPU_CSR_RSVD	0xe0e0fce0

#define FPU_CSR_RSVD	0xe0e0fce0