Commit 38eb21a5 authored by Akhil R's avatar Akhil R Committed by Thierry Reding
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dt-bindings: Add headers for Tegra234 PWM 



Add dt-bindings header files for PWM of Tegra234

Signed-off-by: default avatarAkhil R <akhilrajeev@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent bb747bec

include/dt-bindings/clock/tegra234-clock.h

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@@ -38,6 +38,22 @@ 
#define TEGRA234_CLK_I2C9			55U

#define TEGRA234_CLK_I2C9			55U

/** @brief PLLP clk output */

/** @brief PLLP clk output */

#define TEGRA234_CLK_PLLP_OUT0			102U

#define TEGRA234_CLK_PLLP_OUT0			102U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */

#define TEGRA234_CLK_PWM1			105U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */

#define TEGRA234_CLK_PWM2			106U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */

#define TEGRA234_CLK_PWM3			107U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */

#define TEGRA234_CLK_PWM4			108U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */

#define TEGRA234_CLK_PWM5			109U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */

#define TEGRA234_CLK_PWM6			110U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */

#define TEGRA234_CLK_PWM7			111U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */

#define TEGRA234_CLK_PWM8			112U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */

#define TEGRA234_CLK_SDMMC4			123U

#define TEGRA234_CLK_SDMMC4			123U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */

include/dt-bindings/reset/tegra234-reset.h

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@@ -18,6 +18,14 @@ 
#define TEGRA234_RESET_I2C7			33U

#define TEGRA234_RESET_I2C7			33U

#define TEGRA234_RESET_I2C8			34U

#define TEGRA234_RESET_I2C8			34U

#define TEGRA234_RESET_I2C9			35U

#define TEGRA234_RESET_I2C9			35U

#define TEGRA234_RESET_PWM1			68U

#define TEGRA234_RESET_PWM2			69U

#define TEGRA234_RESET_PWM3			70U

#define TEGRA234_RESET_PWM4			71U

#define TEGRA234_RESET_PWM5			72U

#define TEGRA234_RESET_PWM6			73U

#define TEGRA234_RESET_PWM7			74U

#define TEGRA234_RESET_PWM8			75U

#define TEGRA234_RESET_SDMMC4			85U

#define TEGRA234_RESET_SDMMC4			85U

#define TEGRA234_RESET_UARTA			100U

#define TEGRA234_RESET_UARTA			100U