Commit 391e20d8 authored by Duke Du's avatar Duke Du Committed by Alex Deucher
Browse files

drm/amd/display: add display write back(DWB) 



Signed-off-by: default avatarDuke Du <Duke.Du@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e8cd2643

drivers/gpu/drm/amd/display/dc/core/dc.c

+10 −0
Original line number Diff line number Diff line
@@ -1749,6 +1749,16 @@ struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index) 
	return core_dc->links[link_index];

}



struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe)

{

	struct core_dc *core_dc = DC_TO_CORE(dc);

	if ((pipe >= dwb_pipe0) && (pipe < dwb_pipe_max_num)) {

		return core_dc->res_pool->dwbc[(int)pipe];

	} else {

		return NULL;

	}

}



const struct graphics_object_id dc_get_link_id_at_index(

	struct dc *dc, uint32_t link_index)

{

drivers/gpu/drm/amd/display/dc/dc.h

+2 −0
Original line number Diff line number Diff line
@@ -797,6 +797,8 @@ const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); 
 */

struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index);



struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe);



/* Return id of physical connector represented by a dc_link at link_index.*/

const struct graphics_object_id dc_get_link_id_at_index(

		struct dc *dc, uint32_t link_index);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

+86 −1
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ 


#include "dce_clock_source.h"



#include "core_dc.h"

#include "reg_helper.h"



#define REG(reg)\
@@ -602,6 +603,89 @@ static uint32_t dce110_get_pix_clk_dividers( 
	return pll_calc_error;

}



static uint32_t dce110_get_pll_pixel_rate_in_hz(

	struct clock_source *cs,

	struct pixel_clk_params *pix_clk_params,

	struct pll_settings *pll_settings)

{

	uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

	struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc);

	struct validate_context *context = dc_core->current_context;

	struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst];



	/* This function need separate to different DCE version, before separate, just use pixel clock */

	return pipe_ctx->stream->phy_pix_clk;

}



static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll(

	struct clock_source *cs,

	struct pixel_clk_params *pix_clk_params,

	struct pll_settings *pll_settings)

{

	uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

	struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc);

	struct validate_context *context = dc_core->current_context;

	struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst];



	/* This function need separate to different DCE version, before separate, just use pixel clock */

	return pipe_ctx->stream->phy_pix_clk;

}



static uint32_t dce110_get_d_to_pixel_rate_in_hz(

	struct clock_source *cs,

	struct pixel_clk_params *pix_clk_params,

	struct pll_settings *pll_settings)

{

	uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);

	int dto_enabled = 0;

	struct fixed31_32 pix_rate;



	REG_GET(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, &dto_enabled);



	if (dto_enabled) {

		uint32_t phase = 0;

		uint32_t modulo = 0;

		REG_GET(PHASE[inst], DP_DTO0_PHASE, &phase);

		REG_GET(MODULO[inst], DP_DTO0_MODULO, &modulo);



		if (modulo == 0) {

			return 0;

		}



		pix_rate = dal_fixed31_32_from_int(clk_src->ref_freq_khz);

		pix_rate = dal_fixed31_32_mul_int(pix_rate, 1000);

		pix_rate = dal_fixed31_32_mul_int(pix_rate, phase);

		pix_rate = dal_fixed31_32_div_int(pix_rate, modulo);



		return dal_fixed31_32_round(pix_rate);

	} else {

		return dce110_get_dp_pixel_rate_from_combo_phy_pll(cs, pix_clk_params, pll_settings);

	}

}



static uint32_t dce110_get_pix_rate_in_hz(

	struct clock_source *cs,

	struct pixel_clk_params *pix_clk_params,

	struct pll_settings *pll_settings)

{

	uint32_t pix_rate = 0;

	switch (pix_clk_params->signal_type) {

	case	SIGNAL_TYPE_DISPLAY_PORT:

	case	SIGNAL_TYPE_DISPLAY_PORT_MST:

	case	SIGNAL_TYPE_EDP:

	case	SIGNAL_TYPE_VIRTUAL:

		pix_rate = dce110_get_d_to_pixel_rate_in_hz(cs, pix_clk_params, pll_settings);

		break;

	case	SIGNAL_TYPE_HDMI_TYPE_A:

	default:

		pix_rate = dce110_get_pll_pixel_rate_in_hz(cs, pix_clk_params, pll_settings);

		break;

	}



	return pix_rate;

}



static bool disable_spread_spectrum(struct dce110_clk_src *clk_src)

{

	enum bp_result result;
@@ -962,7 +1046,8 @@ static bool dce110_clock_source_power_down( 
static const struct clock_source_funcs dce110_clk_src_funcs = {

	.cs_power_down = dce110_clock_source_power_down,

	.program_pix_clk = dce110_program_pix_clk,

	.get_pix_clk_dividers = dce110_get_pix_clk_dividers

	.get_pix_clk_dividers = dce110_get_pix_clk_dividers,

	.get_pix_rate_in_hz = dce110_get_pix_rate_in_hz

};



static void get_ss_info_from_atombios(

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

+8 −0
Original line number Diff line number Diff line
@@ -55,6 +55,8 @@ 
	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\

	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)



#if defined(CONFIG_DRM_AMD_DC_DCN1_0)



#define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \

		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\

		SRII(PHASE, DP_DTO, 0),\
@@ -71,9 +73,13 @@ 
		SRII(PIXEL_RATE_CNTL, OTG, 3)



#define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\

	CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\

	CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\

	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\

	CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)



#endif



#define CS_REG_FIELD_LIST(type) \

	type PLL_REF_DIV_SRC; \

	type DCCG_DEEP_COLOR_CNTL1; \
@@ -81,6 +87,8 @@ 
	type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \

	type PLL_POST_DIV_PIXCLK; \

	type PLL_REF_DIV; \

	type DP_DTO0_PHASE; \

	type DP_DTO0_MODULO; \

	type DP_DTO0_ENABLE;



struct dce110_clk_src_shift {

drivers/gpu/drm/amd/display/dc/dcn10/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 


DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \

		dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \

		dcn10_mem_input.o dcn10_mpc.o

		dcn10_mem_input.o dcn10_mpc.o dcn10_dwb.o



AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))