Commit 396eb69c authored by Christoph Hellwig's avatar Christoph Hellwig Committed by Linus Torvalds
Browse files

riscv: use asm-generic/cacheflush.h 



RISC-V needs almost no cache flushing routines of its own.  Rely on
asm-generic/cacheflush.h for the defaults.

Also remove the pointless __KERNEL__ ifdef while we're at it.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Reviewed-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
Acked-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Link: http://lkml.kernel.org/r/20200515143646.3857579-18-hch@lst.de


Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 5019f760

arch/riscv/include/asm/cacheflush.h

+3 −59
Original line number Diff line number Diff line
@@ -8,65 +8,6 @@ 


#include <linux/mm.h>



#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0



/*

 * The cache doesn't need to be flushed when TLB entries change when

 * the cache is mapped to physical memory, not virtual memory

 */

static inline void flush_cache_all(void)

{

}



static inline void flush_cache_mm(struct mm_struct *mm)

{

}



static inline void flush_cache_dup_mm(struct mm_struct *mm)

{

}



static inline void flush_cache_range(struct vm_area_struct *vma,

				     unsigned long start,

				     unsigned long end)

{

}



static inline void flush_cache_page(struct vm_area_struct *vma,

				    unsigned long vmaddr,

				    unsigned long pfn)

{

}



static inline void flush_dcache_mmap_lock(struct address_space *mapping)

{

}



static inline void flush_dcache_mmap_unlock(struct address_space *mapping)

{

}



static inline void flush_icache_page(struct vm_area_struct *vma,

				     struct page *page)

{

}



static inline void flush_cache_vmap(unsigned long start, unsigned long end)

{

}



static inline void flush_cache_vunmap(unsigned long start, unsigned long end)

{

}



#define copy_to_user_page(vma, page, vaddr, dst, src, len) \

	do { \

		memcpy(dst, src, len); \

		flush_icache_user_range(vma, page, vaddr, len); \

	} while (0)

#define copy_from_user_page(vma, page, vaddr, dst, src, len) \

	memcpy(dst, src, len)



static inline void local_flush_icache_all(void)

{

	asm volatile ("fence.i" ::: "memory");
@@ -79,6 +20,7 @@ static inline void flush_dcache_page(struct page *page) 
	if (test_bit(PG_dcache_clean, &page->flags))

		clear_bit(PG_dcache_clean, &page->flags);

}

#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1



/*

 * RISC-V doesn't have an instruction to flush parts of the instruction cache,
@@ -105,4 +47,6 @@ void flush_icache_mm(struct mm_struct *mm, bool local); 
#define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL

#define SYS_RISCV_FLUSH_ICACHE_ALL   (SYS_RISCV_FLUSH_ICACHE_LOCAL)



#include <asm-generic/cacheflush.h>



#endif /* _ASM_RISCV_CACHEFLUSH_H */