Loading drivers/crypto/ixp4xx_crypto.c +24 −19 Original line number Diff line number Diff line Loading @@ -213,6 +213,7 @@ static const struct ix_hash_algo hash_alg_md5 = { .icv = "\x01\x23\x45\x67\x89\xAB\xCD\xEF" "\xFE\xDC\xBA\x98\x76\x54\x32\x10", }; static const struct ix_hash_algo hash_alg_sha1 = { .cfgword = 0x00000005, .icv = "\x67\x45\x23\x01\xEF\xCD\xAB\x89\x98\xBA" Loading Loading @@ -260,6 +261,7 @@ static inline const struct ix_hash_algo *ix_hash(struct crypto_tfm *tfm) static int setup_crypt_desc(void) { struct device *dev = &pdev->dev; BUILD_BUG_ON(sizeof(struct crypt_ctl) != 64); crypt_virt = dma_alloc_coherent(dev, NPE_QLEN * sizeof(struct crypt_ctl), Loading Loading @@ -438,6 +440,7 @@ static void crypto_done_action(unsigned long arg) for (i = 0; i < 4; i++) { dma_addr_t phys = qmgr_get_entry(RECV_QID); if (!phys) return; one_packet(phys); Loading Loading @@ -619,6 +622,7 @@ static int init_tfm_aead(struct crypto_aead *tfm) static void exit_tfm(struct crypto_tfm *tfm) { struct ixp_ctx *ctx = crypto_tfm_ctx(tfm); free_sa_dir(&ctx->encrypt); free_sa_dir(&ctx->decrypt); } Loading Loading @@ -814,9 +818,9 @@ static int setup_cipher(struct crypto_tfm *tfm, int encrypt, } dir->npe_ctx_idx = sizeof(cipher_cfg) + key_len; dir->npe_mode |= NPE_OP_CRYPT_ENABLE; if ((cipher_cfg & MOD_AES) && !encrypt) { if ((cipher_cfg & MOD_AES) && !encrypt) return gen_rev_aes_key(tfm); } return 0; } Loading Loading @@ -971,6 +975,7 @@ static int ablk_perform(struct skcipher_request *req, int encrypt) } if (req->src != req->dst) { struct buffer_desc dst_hook; crypt->mode |= NPE_OP_NOT_IN_PLACE; /* This was never tested by Intel * for more than one dst buffer, I think. */ Loading Loading
drivers/crypto/ixp4xx_crypto.c +24 −19 Original line number Diff line number Diff line Loading @@ -213,6 +213,7 @@ static const struct ix_hash_algo hash_alg_md5 = { .icv = "\x01\x23\x45\x67\x89\xAB\xCD\xEF" "\xFE\xDC\xBA\x98\x76\x54\x32\x10", }; static const struct ix_hash_algo hash_alg_sha1 = { .cfgword = 0x00000005, .icv = "\x67\x45\x23\x01\xEF\xCD\xAB\x89\x98\xBA" Loading Loading @@ -260,6 +261,7 @@ static inline const struct ix_hash_algo *ix_hash(struct crypto_tfm *tfm) static int setup_crypt_desc(void) { struct device *dev = &pdev->dev; BUILD_BUG_ON(sizeof(struct crypt_ctl) != 64); crypt_virt = dma_alloc_coherent(dev, NPE_QLEN * sizeof(struct crypt_ctl), Loading Loading @@ -438,6 +440,7 @@ static void crypto_done_action(unsigned long arg) for (i = 0; i < 4; i++) { dma_addr_t phys = qmgr_get_entry(RECV_QID); if (!phys) return; one_packet(phys); Loading Loading @@ -619,6 +622,7 @@ static int init_tfm_aead(struct crypto_aead *tfm) static void exit_tfm(struct crypto_tfm *tfm) { struct ixp_ctx *ctx = crypto_tfm_ctx(tfm); free_sa_dir(&ctx->encrypt); free_sa_dir(&ctx->decrypt); } Loading Loading @@ -814,9 +818,9 @@ static int setup_cipher(struct crypto_tfm *tfm, int encrypt, } dir->npe_ctx_idx = sizeof(cipher_cfg) + key_len; dir->npe_mode |= NPE_OP_CRYPT_ENABLE; if ((cipher_cfg & MOD_AES) && !encrypt) { if ((cipher_cfg & MOD_AES) && !encrypt) return gen_rev_aes_key(tfm); } return 0; } Loading Loading @@ -971,6 +975,7 @@ static int ablk_perform(struct skcipher_request *req, int encrypt) } if (req->src != req->dst) { struct buffer_desc dst_hook; crypt->mode |= NPE_OP_NOT_IN_PLACE; /* This was never tested by Intel * for more than one dst buffer, I think. */ Loading