Commit 3a108387 authored by Le Ma's avatar Le Ma Committed by Alex Deucher
Browse files

drm/amdgpu: do mmhub init for multiple AIDs 



Mmhub on each AID needs to be initialized respectively

Signed-off-by: default avatarLe Ma <le.ma@amd.com>
Acked-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2a47a2d9

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

+348 −261
Original line number Diff line number Diff line
@@ -53,18 +53,27 @@ static u64 mmhub_v1_8_get_fb_location(struct amdgpu_device *adev) 
static void mmhub_v1_8_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

				uint64_t page_table_base)

{

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];



	WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

			    hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));

	struct amdgpu_vmhub *hub;

	int i;



	WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

			    hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base));

	for (i = 0; i < adev->num_aid; i++) {

		hub = &adev->vmhub[AMDGPU_MMHUB0(i)];

		WREG32_SOC15_OFFSET(MMHUB, i,

				    regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

				    hub->ctx_addr_distance * vmid,

				    lower_32_bits(page_table_base));



		WREG32_SOC15_OFFSET(MMHUB, i,

				    regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

				    hub->ctx_addr_distance * vmid,

				    upper_32_bits(page_table_base));

	}

}



static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev)

{

	uint64_t pt_base;

	int i;



	if (adev->gmc.pdb0_bo)

		pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);
@@ -76,89 +85,115 @@ static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev) 
	/* If use GART for FB translation, vmid0 page table covers both

	 * vram and system memory (gart)

	 */

	for (i = 0; i < adev->num_aid; i++) {

		if (adev->gmc.pdb0_bo) {

		WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

			WREG32_SOC15(MMHUB, i,

				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

				     (u32)(adev->gmc.fb_start >> 12));

		WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,

			WREG32_SOC15(MMHUB, i,

				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,

				     (u32)(adev->gmc.fb_start >> 44));



		WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,

			WREG32_SOC15(MMHUB, i,

				     regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,

				     (u32)(adev->gmc.gart_end >> 12));

		WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

			WREG32_SOC15(MMHUB, i,

				     regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

				     (u32)(adev->gmc.gart_end >> 44));



		} else {

		WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

			WREG32_SOC15(MMHUB, i,

				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

				     (u32)(adev->gmc.gart_start >> 12));

		WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,

			WREG32_SOC15(MMHUB, i,

				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,

				     (u32)(adev->gmc.gart_start >> 44));



		WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,

			WREG32_SOC15(MMHUB, i,

				     regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,

				     (u32)(adev->gmc.gart_end >> 12));

		WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

			WREG32_SOC15(MMHUB, i,

				     regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

				     (u32)(adev->gmc.gart_end >> 44));

		}

	}

}



static void mmhub_v1_8_init_system_aperture_regs(struct amdgpu_device *adev)

{

	uint64_t value;

	uint32_t tmp;

	int i;



	for (i = 0; i < adev->num_aid; i++) {

		/* Program the AGP BAR */

	WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BASE, 0);

	WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);

	WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);

		WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BASE, 0);

		WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BOT,

			     adev->gmc.agp_start >> 24);

		WREG32_SOC15(MMHUB, i, regMC_VM_AGP_TOP,

			     adev->gmc.agp_end >> 24);



		if (amdgpu_sriov_vf(adev))

			return;



		/* Program the system aperture low logical page number. */

	WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,

		WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,

			min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);



	WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

		WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

			max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);



		/* In the case squeezing vram into GART aperture, we don't use

		 * FB aperture and AGP aperture. Disable them.

		 */

		if (adev->gmc.pdb0_bo) {

		WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, 0xFFFFFF);

		WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, 0);

		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, 0);

		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);

		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);

		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);

			WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BOT, 0xFFFFFF);

			WREG32_SOC15(MMHUB, i, regMC_VM_AGP_TOP, 0);

			WREG32_SOC15(MMHUB, i, regMC_VM_FB_LOCATION_TOP, 0);

			WREG32_SOC15(MMHUB, i, regMC_VM_FB_LOCATION_BASE,

				     0x00FFFFFF);

			WREG32_SOC15(MMHUB, i,

				     regMC_VM_SYSTEM_APERTURE_LOW_ADDR,

				     0x3FFFFFFF);

			WREG32_SOC15(MMHUB, i,

				     regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);

		}

	if (amdgpu_sriov_vf(adev))

		return;



		/* Set default page address. */

		value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);

	WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

		WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

			     (u32)(value >> 12));

	WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

		WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

			     (u32)(value >> 44));



		/* Program "protection fault". */

	WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,

		WREG32_SOC15(MMHUB, i,

			     regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,

			     (u32)(adev->dummy_page_addr >> 12));

	WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,

		WREG32_SOC15(MMHUB, i,

			     regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,

			     (u32)((u64)adev->dummy_page_addr >> 44));



	tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2);

		tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2);

		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,

				    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);

	WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);

		WREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);

	}

}



static void mmhub_v1_8_init_tlb_regs(struct amdgpu_device *adev)

{

	uint32_t tmp;

	int i;



	/* Setup TLB control */

	tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);

	for (i = 0; i < adev->num_aid; i++) {

		tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);



	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,

				    1);

		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

				    SYSTEM_ACCESS_MODE, 3);

		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

				    ENABLE_ADVANCED_DRIVER_MODEL, 1);

		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
@@ -167,32 +202,40 @@ static void mmhub_v1_8_init_tlb_regs(struct amdgpu_device *adev) 
				    MTYPE, MTYPE_UC);/* XXX for emulation. */

		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);



	WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);

		WREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL, tmp);

	}

}



static void mmhub_v1_8_init_cache_regs(struct amdgpu_device *adev)

{

	uint32_t tmp;

	int i;



	if (amdgpu_sriov_vf(adev))

		return;



	/* Setup L2 cache */

	tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);

	for (i = 0; i < adev->num_aid; i++) {

		tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,

				    ENABLE_L2_FRAGMENT_PROCESSING, 1);

		/* XXX for emulation, Refer to closed source code.*/

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,

				    L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION,

				    0);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

	WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);



	tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,

				    CONTEXT1_IDENTITY_ACCESS_MODE, 1);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,

				    IDENTITY_MODE_FRAGMENT_SIZE, 0);

		WREG32_SOC15(MMHUB, i, regVM_L2_CNTL, tmp);



		tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL2);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS,

				    1);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

	WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2, tmp);

		WREG32_SOC15(MMHUB, i, regVM_L2_CNTL2, tmp);



		tmp = regVM_L2_CNTL3_DEFAULT;

		if (adev->gmc.translate_further) {
@@ -204,7 +247,7 @@ static void mmhub_v1_8_init_cache_regs(struct amdgpu_device *adev) 
			tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

					    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);

		}

	WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, tmp);

		WREG32_SOC15(MMHUB, i, regVM_L2_CNTL3, tmp);



		tmp = regVM_L2_CNTL4_DEFAULT;

		if (adev->gmc.xgmi.connected_to_cpu) {
@@ -218,45 +261,64 @@ static void mmhub_v1_8_init_cache_regs(struct amdgpu_device *adev) 
			tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

					    VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

		}

	WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL4, tmp);

		WREG32_SOC15(MMHUB, i, regVM_L2_CNTL4, tmp);

 	}

}



static void mmhub_v1_8_enable_system_domain(struct amdgpu_device *adev)

{

	uint32_t tmp;

	int i;



	tmp = RREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL);

	for (i = 0; i < adev->num_aid; i++) {

		tmp = RREG32_SOC15(MMHUB, i, regVM_CONTEXT0_CNTL);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,

				adev->gmc.vmid0_page_table_depth);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,

		tmp = REG_SET_FIELD(tmp,

				    VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,

				    adev->gmc.vmid0_page_table_block_size);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,

				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);

	WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL, tmp);

		WREG32_SOC15(MMHUB, i, regVM_CONTEXT0_CNTL, tmp);

	}

}



static void mmhub_v1_8_disable_identity_aperture(struct amdgpu_device *adev)

{

	int i;



	if (amdgpu_sriov_vf(adev))

		return;



	WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 0xFFFFFFFF);

	WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 0x0000000F);

	for (i = 0; i < adev->num_aid; i++) {

		WREG32_SOC15(MMHUB, i,

			     regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,

			     0XFFFFFFFF);

		WREG32_SOC15(MMHUB, i,

			     regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,

			     0x0000000F);



	WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);

	WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);

		WREG32_SOC15(MMHUB, i,

			     regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,

			     0);

		WREG32_SOC15(MMHUB, i,

			     regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,

			     0);



	WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);

	WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);

		WREG32_SOC15(MMHUB, i,

			     regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);

		WREG32_SOC15(MMHUB, i,

			     regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);

	}

}



static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)

{

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];

	struct amdgpu_vmhub *hub;

	unsigned num_level, block_size;

	uint32_t tmp;

	int i;

	int i, j;



	num_level = adev->vm_manager.num_level;

	block_size = adev->vm_manager.block_size;
@@ -265,16 +327,19 @@ static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev) 
	else

		block_size -= 9;



	for (j = 0; j < adev->num_aid; j++) {

		hub = &adev->vmhub[AMDGPU_MMHUB0(j)];

		for (i = 0; i <= 14; i++) {

		tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

				    num_level);

			tmp = RREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT1_CNTL,

						  i);

			tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

					    ENABLE_CONTEXT, 1);

			tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

					    PAGE_TABLE_DEPTH, num_level);

			tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

			tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,

				    1);

				DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

			tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

			tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
@@ -288,39 +353,49 @@ static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev) 
			tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

					    PAGE_TABLE_BLOCK_SIZE,

					    block_size);

		/* On 9.4.3, XNACK can be enabled in the SQ per-process.

		 * Retry faults need to be enabled for that to work.

			/* On 9.4.3, XNACK can be enabled in the SQ

			 * per-process. Retry faults need to be enabled for

			 * that to work.

			 */

			tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,

				    1);

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL,

				RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 1);

			WREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT1_CNTL,

					    i * hub->ctx_distance, tmp);

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,

			WREG32_SOC15_OFFSET(MMHUB, j,

				regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,

				i * hub->ctx_addr_distance, 0);

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,

			WREG32_SOC15_OFFSET(MMHUB, j,

				regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,

				i * hub->ctx_addr_distance, 0);

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,

			WREG32_SOC15_OFFSET(MMHUB, j,

				regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,

				i * hub->ctx_addr_distance,

				lower_32_bits(adev->vm_manager.max_pfn - 1));

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,

			WREG32_SOC15_OFFSET(MMHUB, j,

				regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,

				i * hub->ctx_addr_distance,

				upper_32_bits(adev->vm_manager.max_pfn - 1));

		}

	}

}



static void mmhub_v1_8_program_invalidation(struct amdgpu_device *adev)

{

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];

	unsigned i;

	struct amdgpu_vmhub *hub;

	unsigned i, j;



	for (j = 0; j < adev->num_aid; j++) {

		hub = &adev->vmhub[AMDGPU_MMHUB0(j)];

		for (i = 0; i < 18; ++i) {

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,

			WREG32_SOC15_OFFSET(MMHUB, j,

					regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,

					i * hub->eng_addr_distance, 0xffffffff);

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,

			WREG32_SOC15_OFFSET(MMHUB, j,

					regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,

					i * hub->eng_addr_distance, 0x1f);

		}

	}

}



static int mmhub_v1_8_gart_enable(struct amdgpu_device *adev)

{
@@ -352,28 +427,33 @@ static int mmhub_v1_8_gart_enable(struct amdgpu_device *adev) 


static void mmhub_v1_8_gart_disable(struct amdgpu_device *adev)

{

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];

	struct amdgpu_vmhub *hub;

	u32 tmp;

	u32 i;

	u32 i, j;



	/* Disable all tables */

	for (j = 0; j < adev->num_aid; j++) {

		hub = &adev->vmhub[AMDGPU_MMHUB0(j)];

		for (i = 0; i < 16; i++)

		WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL,

			WREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT0_CNTL,

					    i * hub->ctx_distance, 0);



		/* Setup TLB control */

	tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

		tmp = RREG32_SOC15(MMHUB, j, regMC_VM_MX_L1_TLB_CNTL);

		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,

				    0);

		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

				    ENABLE_ADVANCED_DRIVER_MODEL, 0);

	WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);

		WREG32_SOC15(MMHUB, j, regMC_VM_MX_L1_TLB_CNTL, tmp);



		if (!amdgpu_sriov_vf(adev)) {

			/* Setup L2 cache */

		tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

		WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);

		WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, 0);

			tmp = RREG32_SOC15(MMHUB, j, regVM_L2_CNTL);

			tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE,

					    0);

			WREG32_SOC15(MMHUB, j, regVM_L2_CNTL, tmp);

			WREG32_SOC15(MMHUB, j, regVM_L2_CNTL3, 0);

		}

	}

}
@@ -386,11 +466,13 @@ static void mmhub_v1_8_gart_disable(struct amdgpu_device *adev) 
static void mmhub_v1_8_set_fault_enable_default(struct amdgpu_device *adev, bool value)

{

	u32 tmp;

	int i;



	if (amdgpu_sriov_vf(adev))

		return;



	tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);

	for (i = 0; i < adev->num_aid; i++) {

		tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL);

		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
@@ -421,18 +503,21 @@ static void mmhub_v1_8_set_fault_enable_default(struct amdgpu_device *adev, bool 
					    CRASH_ON_RETRY_FAULT, 1);

		}



	WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL, tmp);

		WREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL, tmp);

	}

}



static void mmhub_v1_8_init(struct amdgpu_device *adev)

{

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];

	struct amdgpu_vmhub *hub;

	int i;



	for (i = 0; i < adev->num_aid; i++) {

		hub = &adev->vmhub[AMDGPU_MMHUB0(i)];



	hub->ctx0_ptb_addr_lo32 =

		SOC15_REG_OFFSET(MMHUB, 0,

		hub->ctx0_ptb_addr_lo32 = SOC15_REG_OFFSET(MMHUB, 0,

			regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);

	hub->ctx0_ptb_addr_hi32 =

		SOC15_REG_OFFSET(MMHUB, 0,

		hub->ctx0_ptb_addr_hi32 = SOC15_REG_OFFSET(MMHUB, 0,

			regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);

		hub->vm_inv_eng0_req =

			SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_REQ);
@@ -440,18 +525,20 @@ static void mmhub_v1_8_init(struct amdgpu_device *adev) 
			SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ACK);

		hub->vm_context0_cntl =

			SOC15_REG_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL);

	hub->vm_l2_pro_fault_status =

		SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_STATUS);

	hub->vm_l2_pro_fault_cntl =

		SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);

		hub->vm_l2_pro_fault_status = SOC15_REG_OFFSET(MMHUB, 0,

			regVM_L2_PROTECTION_FAULT_STATUS);

		hub->vm_l2_pro_fault_cntl = SOC15_REG_OFFSET(MMHUB, 0,

			regVM_L2_PROTECTION_FAULT_CNTL);



		hub->ctx_distance = regVM_CONTEXT1_CNTL - regVM_CONTEXT0_CNTL;

	hub->ctx_addr_distance = regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -

		hub->ctx_addr_distance =

			regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -

			regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;

	hub->eng_distance = regVM_INVALIDATE_ENG1_REQ - regVM_INVALIDATE_ENG0_REQ;

		hub->eng_distance = regVM_INVALIDATE_ENG1_REQ -

			regVM_INVALIDATE_ENG0_REQ;

		hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -

			regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;



	}

}



static int mmhub_v1_8_set_clockgating(struct amdgpu_device *adev,