Commit 3a372bed authored by Hugo Hu's avatar Hugo Hu Committed by Alex Deucher
Browse files

drm/amd/display: correct eDP T9 delay 



[Why]
The current end of T9 delay is relay on polling
sink status by DPCD. But the polling for sink
status change after NoVideoStream_flag set to 0.

[How]
Add function edp_add_delay_for_T9 to add T9 delay.
Move the sink status polling after blank.

Signed-off-by: default avatarHugo Hu <hugo.hu@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cae78e03

drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

+8 −5
Original line number Diff line number Diff line
@@ -156,6 +156,13 @@ void dp_enable_link_phy( 
	dp_receiver_power_ctrl(link, true);

}



void edp_add_delay_for_T9(struct dc_link *link)

{

	if (link->local_sink &&

			link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)

		udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000);

}



bool edp_receiver_ready_T9(struct dc_link *link)

{

	unsigned int tries = 0;
@@ -178,10 +185,6 @@ bool edp_receiver_ready_T9(struct dc_link *link) 
		} while (++tries < 50);

	}



	if (link->local_sink &&

			link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)

		udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000);



	return result;

}

bool edp_receiver_ready_T7(struct dc_link *link)

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+8 −8
Original line number Diff line number Diff line
@@ -992,8 +992,6 @@ void dce110_edp_backlight_control( 


	link_transmitter_control(ctx->dc_bios, &cntl);







	if (enable && link->dpcd_sink_ext_caps.bits.oled)

		msleep(OLED_POST_T7_DELAY);
@@ -1004,7 +1002,7 @@ void dce110_edp_backlight_control( 


	/*edp 1.2*/

	if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)

		edp_receiver_ready_T9(link);

		edp_add_delay_for_T9(link);



	if (!enable && link->dpcd_sink_ext_caps.bits.oled)

		msleep(OLED_PRE_T11_DELAY);
@@ -1145,12 +1143,14 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 
	if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

		pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);



		if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {

			/*

			 * After output is idle pattern some sinks need time to recognize the stream

			 * has changed or they enter protection state and hang.

			 */

		if (!dc_is_embedded_signal(pipe_ctx->stream->signal))

			msleep(60);

		} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)

			edp_receiver_ready_T9(link);

	}



}

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ void dp_enable_link_phy( 
	const struct dc_link_settings *link_settings);



void dp_receiver_power_ctrl(struct dc_link *link, bool on);

void edp_add_delay_for_T9(struct dc_link *link);

bool edp_receiver_ready_T9(struct dc_link *link);

bool edp_receiver_ready_T7(struct dc_link *link);