Commit 3e5b4cdf authored by Jacky Liao's avatar Jacky Liao Committed by Alex Deucher
Browse files

drm/amd/display: Add MPC memory shutdown support for DCN3 



[Why]
The MPC memory blocks in DCN3 should be powered down completely when
they are not in use. This will reduce power consumption.

[How]
This commits changes behaviour for dcn3 and does the following:
1. Write to MPC_RMU<X>_LOW_PWR_MODE and MPCC_OGAM_MEM_LOW_PWR_MODE to
   automatically shut down memory when not in use
2. mpc3_power_on_shaper_3dlut and mpc3_power_on_ogam_lut are called
   to disable force power on when configuration finishes
3. Added a debug option to allow this behaviour to be turned off

Signed-off-by: default avatarJacky Liao <ziyu.liao@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 585e7ced

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -506,6 +506,7 @@ struct dc_debug_options { 
	bool disable_dsc;

	bool enable_dram_clock_change_one_display_vactive;

	bool force_ignore_link_settings;

	bool enable_mpc_mem_powerdown: 1;

};



struct dc_debug_data {

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c

+53 −3
Original line number Diff line number Diff line
@@ -143,9 +143,17 @@ static void mpc3_power_on_ogam_lut( 
{

	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);



	if (mpc->ctx->dc->debug.enable_mpc_mem_powerdown) {

		// Force power on

		REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_DIS, power_on == true ? 1:0);

		// Wait for confirmation when powering on

		if (power_on)

			REG_WAIT(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_STATE, 0, 10, 10);

	} else {

		REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,

				MPCC_OGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1);

	}

}



static void mpc3_configure_ogam_lut(

		struct mpc *mpc, int mpcc_id,
@@ -360,6 +368,9 @@ void mpc3_set_output_gamma( 
	/*we need to program 2 fields here as apposed to 1*/

	REG_UPDATE(MPCC_OGAM_CONTROL[mpcc_id],

			MPCC_OGAM_SELECT, next_mode == LUT_RAM_A ? 0:1);



	if (mpc->ctx->dc->debug.enable_mpc_mem_powerdown)

		mpc3_power_on_ogam_lut(mpc, mpcc_id, false);

}



void mpc3_set_denorm(
@@ -801,16 +812,28 @@ static void mpc3_power_on_shaper_3dlut( 
	uint32_t power_status_shaper = 2;

	uint32_t power_status_3dlut  = 2;

	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

	int max_retries = 10;



	if (rmu_idx == 0) {

		REG_SET(MPC_RMU_MEM_PWR_CTRL, 0,

			MPC_RMU0_MEM_PWR_DIS, power_on == true ? 1:0);

		/* wait for memory to fully power up */

		if (power_on && mpc->ctx->dc->debug.enable_mpc_mem_powerdown) {

			REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);

			REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);

		}



		/*read status is not mandatory, it is just for debugging*/

		REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, &power_status_shaper);

		REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, &power_status_3dlut);

	} else if (rmu_idx == 1) {

		REG_SET(MPC_RMU_MEM_PWR_CTRL, 0,

			MPC_RMU1_MEM_PWR_DIS, power_on == true ? 1:0);

		if (power_on && mpc->ctx->dc->debug.enable_mpc_mem_powerdown) {

			REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);

			REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);

		}



		REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, &power_status_shaper);

		REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, &power_status_3dlut);

	}
@@ -838,6 +861,10 @@ bool mpc3_program_shaper( 
		REG_SET(SHAPER_CONTROL[rmu_idx], 0, MPC_RMU_SHAPER_LUT_MODE, 0);

		return false;

	}



	if (mpc->ctx->dc->debug.enable_mpc_mem_powerdown)

		mpc3_power_on_shaper_3dlut(mpc, rmu_idx, true);



	current_mode = mpc3_get_shaper_current(mpc, rmu_idx);



	if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
@@ -1196,6 +1223,9 @@ bool mpc3_program_3dlut( 
	mpc3_set_3dlut_mode(mpc, mode, is_12bits_color_channel,

					is_17x17x17, rmu_idx);



	if (mpc->ctx->dc->debug.enable_mpc_mem_powerdown)

		mpc3_power_on_shaper_3dlut(mpc, rmu_idx, false);



	return true;

}
@@ -1349,11 +1379,31 @@ int mpcc3_release_rmu(struct mpc *mpc, int mpcc_id) 


}



static void mpc3_mpc_init(struct mpc *mpc)

{

	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

	int mpcc_id;



	mpc1_mpc_init(mpc);



	if (mpc->ctx->dc->debug.enable_mpc_mem_powerdown) {

		if (mpc30->mpc_mask->MPC_RMU0_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPC_RMU1_MEM_LOW_PWR_MODE) {

			REG_UPDATE(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, 3);

			REG_UPDATE(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_LOW_PWR_MODE, 3);

		}



		if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) {

			for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++)

				REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3);

		}

	}

}



const struct mpc_funcs dcn30_mpc_funcs = {

	.read_mpcc_state = mpc1_read_mpcc_state,

	.insert_plane = mpc1_insert_plane,

	.remove_mpcc = mpc1_remove_mpcc,

	.mpc_init = mpc1_mpc_init,

	.mpc_init = mpc3_mpc_init,

	.mpc_init_single_inst = mpc1_mpc_init_single_inst,

	.update_blending = mpc2_update_blending,

	.cursor_lock = mpc1_cursor_lock,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h

+9 −0
Original line number Diff line number Diff line
@@ -300,6 +300,7 @@ 
	SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\

	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\

	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\

	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\

	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\

	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\

	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
@@ -406,6 +407,8 @@ 
	SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\

	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\

	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\

	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\

	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\

	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\

	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\

	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
@@ -492,10 +495,12 @@ 
	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\

	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\

	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\

	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, mask_sh),\

	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_FORCE, mask_sh),\

	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_DIS, mask_sh),\

	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, mask_sh),\

	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, mask_sh),\

	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_LOW_PWR_MODE, mask_sh),\

	SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_MODE_CURRENT, mask_sh),\

	SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
@@ -519,10 +524,12 @@ 
	type MPC_RMU1_MUX_STATUS; \

	type MPC_RMU0_MEM_PWR_FORCE;\

	type MPC_RMU0_MEM_PWR_DIS;\

	type MPC_RMU0_MEM_LOW_PWR_MODE;\

	type MPC_RMU0_SHAPER_MEM_PWR_STATE;\

	type MPC_RMU0_3DLUT_MEM_PWR_STATE;\

	type MPC_RMU1_MEM_PWR_FORCE;\

	type MPC_RMU1_MEM_PWR_DIS;\

	type MPC_RMU1_MEM_LOW_PWR_MODE;\

	type MPC_RMU1_SHAPER_MEM_PWR_STATE;\

	type MPC_RMU1_3DLUT_MEM_PWR_STATE;\

	type MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; \
@@ -541,6 +548,8 @@ 
	type MPCC_OGAM_LUT_CONFIG_MODE; \

	type MPCC_OGAM_LUT_STATUS; \

	type MPCC_OGAM_RAMA_START_BASE_CNTL_B;\

	type MPCC_OGAM_MEM_LOW_PWR_MODE;\

	type MPCC_OGAM_MEM_PWR_STATE;\

	type MPC_RMU_3DLUT_MODE; \

	type MPC_RMU_3DLUT_SIZE; \

	type MPC_RMU_3DLUT_MODE_CURRENT; \