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Commit 3e6670a2 authored by Xingyu Wu's avatar Xingyu Wu Committed by Conor Dooley
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riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node



Add PLL clocks input from PLL clocks driver in SYSCRG node.

Reviewed-by: default avatarEmil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarXingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 3fcbcfc4
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