Commit 3fc93030 authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Mark Brown
Browse files

ASoC: TWL4030: Syncronize the reg_cache for ANAMICL after the offset cancelation 



The offset cancelation bit in ANAMICL register is self cleanig.
Make sure that the reg_cache holds the same value as the HW
register.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent 6627a653

sound/soc/codecs/twl4030.c

+3 −0
Original line number Diff line number Diff line
@@ -913,6 +913,9 @@ static void twl4030_power_up(struct snd_soc_codec *codec) 
		 ((byte & TWL4030_CNCL_OFFSET_START) ==

		  TWL4030_CNCL_OFFSET_START));



	/* Make sure that the reg_cache has the same value as the HW */

	twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);



	/* anti-pop when changing analog gain */

	regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);

	twl4030_write(codec, TWL4030_REG_MISC_SET_1,