Commit 3ffa6f32 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/gr/gv100-: port smid mapping code from nvgpu 



Essentially ripped verbatim from NVGPU, comments and all, and adapted to
nvkm's structs and style.

- maybe fixes an nvgpu bug though, a small tweak was needed to match RM

v2:
- remove unnecessary WARN_ON

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
parent d94ac9dd

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c

+3 −0
Original line number Diff line number Diff line
@@ -157,6 +157,9 @@ static void 
gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)

{

	struct nvkm_device *device = gr->base.engine.subdev.device;



	tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc);



	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);

	nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm);

	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxtu102.c

+3 −0
Original line number Diff line number Diff line
@@ -34,6 +34,9 @@ static void 
tu102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)

{

	struct nvkm_device *device = gr->base.engine.subdev.device;



	tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc);



	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);

	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);

}

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

+8 −3
Original line number Diff line number Diff line
@@ -1889,10 +1889,11 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) 
	return ret;

}



void

int

gf100_gr_oneinit_sm_id(struct gf100_gr *gr)

{

	int tpc, gpc;



	for (tpc = 0; tpc < gr->tpc_max; tpc++) {

		for (gpc = 0; gpc < gr->gpc_nr; gpc++) {

			if (tpc < gr->tpc_nr[gpc]) {
@@ -1902,6 +1903,8 @@ gf100_gr_oneinit_sm_id(struct gf100_gr *gr) 
			}

		}

	}



	return 0;

}



void
@@ -2019,6 +2022,8 @@ gf100_gr_oneinit(struct nvkm_gr *base) 
			if (gr->ppc_tpc_max < gr->ppc_tpc_nr[i][j])

				gr->ppc_tpc_max = gr->ppc_tpc_nr[i][j];

		}



		gr->ppc_total += gr->ppc_nr[i];

	}



	/* Allocate global context buffers. */
@@ -2046,8 +2051,8 @@ gf100_gr_oneinit(struct nvkm_gr *base) 


	memset(gr->tile, 0xff, sizeof(gr->tile));

	gr->func->oneinit_tiles(gr);

	gr->func->oneinit_sm_id(gr);

	return 0;



	return gr->func->oneinit_sm_id(gr);

}



static int

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h

+6 −3
Original line number Diff line number Diff line
@@ -107,6 +107,7 @@ struct gf100_gr { 
	u8 ppc_tpc_nr[GPC_MAX][4];

	u8 ppc_tpc_min;

	u8 ppc_tpc_max;

	u8 ppc_total;



	struct nvkm_memory *pagepool;

	struct nvkm_memory *bundle_cb;
@@ -141,7 +142,7 @@ struct gf100_gr_func_zbc { 


struct gf100_gr_func {

	void (*oneinit_tiles)(struct gf100_gr *);

	void (*oneinit_sm_id)(struct gf100_gr *);

	int (*oneinit_sm_id)(struct gf100_gr *);

	int (*init)(struct gf100_gr *);

	void (*init_419bd8)(struct gf100_gr *);

	void (*init_gpc_mmu)(struct gf100_gr *);
@@ -191,7 +192,7 @@ struct gf100_gr_func { 


int gf100_gr_rops(struct gf100_gr *);

void gf100_gr_oneinit_tiles(struct gf100_gr *);

void gf100_gr_oneinit_sm_id(struct gf100_gr *);

int gf100_gr_oneinit_sm_id(struct gf100_gr *);

int gf100_gr_init(struct gf100_gr *);

void gf100_gr_init_vsc_stream_master(struct gf100_gr *);

void gf100_gr_init_zcull(struct gf100_gr *);
@@ -228,7 +229,7 @@ int gk20a_gr_aiv_to_init(struct nvkm_blob *, struct gf100_gr_pack **); 
int gk20a_gr_av_to_method(struct nvkm_blob *, struct gf100_gr_pack **);



void gm200_gr_oneinit_tiles(struct gf100_gr *);

void gm200_gr_oneinit_sm_id(struct gf100_gr *);

int gm200_gr_oneinit_sm_id(struct gf100_gr *);

int gm200_gr_rops(struct gf100_gr *);

void gm200_gr_init_num_active_ltcs(struct gf100_gr *);

void gm200_gr_init_ds_hww_esr_2(struct gf100_gr *);
@@ -245,6 +246,8 @@ extern const struct gf100_gr_func_zbc gp102_gr_zbc; 


extern const struct gf100_gr_func gp107_gr;



int gv100_gr_oneinit_sm_id(struct gf100_gr *);

u32 gv100_gr_nonpes_aware_tpc(struct gf100_gr *gr, u32 gpc, u32 tpc);

void gv100_gr_init_419bd8(struct gf100_gr *);

void gv100_gr_init_504430(struct gf100_gr *, int, int);

void gv100_gr_init_shader_exceptions(struct gf100_gr *, int, int);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c

+2 −2
Original line number Diff line number Diff line
@@ -148,11 +148,11 @@ gm200_gr_tile_map_2_8[] = { 
	0, 1, 1, 0, 0, 1, 1, 0,

};



void

int

gm200_gr_oneinit_sm_id(struct gf100_gr *gr)

{

	/*XXX: There's a different algorithm here I've not yet figured out. */

	gf100_gr_oneinit_sm_id(gr);

	return gf100_gr_oneinit_sm_id(gr);

}



void