Commit 40111ec2 authored by Felix Kuehling's avatar Felix Kuehling Committed by Alex Deucher
Browse files

drm/amdgpu: Clean up KFD VMID assignment 



The KFD VMID assignment was hard-coded in a few places. Consolidate that in
a single variable adev->vm_manager.first_kfd_vmid. The value is still
assigned in gmc-ip-version-specific code.

Signed-off-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a71a4f50

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+5 −7
Original line number Diff line number Diff line
@@ -31,8 +31,6 @@ 
#include "amdgpu_xgmi.h"

#include <uapi/linux/kfd_ioctl.h>



static const unsigned int compute_vmid_bitmap = 0xFF00;



/* Total memory size in system memory and all GPU VRAM. Used to

 * estimate worst case amount of memory to reserve for page tables

 */
@@ -113,7 +111,9 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 


	if (adev->kfd.dev) {

		struct kgd2kfd_shared_resources gpu_resources = {

			.compute_vmid_bitmap = compute_vmid_bitmap,

			.compute_vmid_bitmap =

				((1 << AMDGPU_NUM_VMID) - 1) -

				((1 << adev->vm_manager.first_kfd_vmid) - 1),

			.num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,

			.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,

			.gpuvm_size = min(adev->vm_manager.max_pfn
@@ -637,10 +637,8 @@ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle) 


bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)

{

	if (adev->kfd.dev) {

		if ((1 << vmid) & compute_vmid_bitmap)

			return true;

	}

	if (adev->kfd.dev)

		return vmid >= adev->vm_manager.first_kfd_vmid;



	return false;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c

+3 −0
Original line number Diff line number Diff line
@@ -574,6 +574,9 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev) 
		INIT_LIST_HEAD(&id_mgr->ids_lru);

		atomic_set(&id_mgr->reserved_vmid_num, 0);



		/* manage only VMIDs not used by KFD */

		id_mgr->num_ids = adev->vm_manager.first_kfd_vmid;



		/* skip over VMID 0, since it is the system VM */

		for (j = 1; j < id_mgr->num_ids; ++j) {

			amdgpu_vmid_reset(adev, i, j);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

+1 −0
Original line number Diff line number Diff line
@@ -324,6 +324,7 @@ struct amdgpu_vm { 
struct amdgpu_vm_manager {

	/* Handling of VMIDs */

	struct amdgpu_vmid_mgr			id_mgr[AMDGPU_MAX_VMHUBS];

	unsigned int				first_kfd_vmid;



	/* Handling of VM fences */

	u64					fence_context;

drivers/gpu/drm/amd/amdgpu/cikd.h

+0 −2
Original line number Diff line number Diff line
@@ -54,8 +54,6 @@ 
#define BONAIRE_GB_ADDR_CONFIG_GOLDEN        0x12010001

#define HAWAII_GB_ADDR_CONFIG_GOLDEN         0x12011003



#define AMDGPU_NUM_OF_VMIDS	8



#define		PIPEID(x)					((x) << 0)

#define		MEID(x)						((x) << 2)

#define		VMID(x)						((x) << 4)

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+2 −4
Original line number Diff line number Diff line
@@ -4512,8 +4512,6 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade 
}



#define DEFAULT_SH_MEM_BASES	(0x6000)

#define FIRST_COMPUTE_VMID	(8)

#define LAST_COMPUTE_VMID	(16)



static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)

{
@@ -4529,7 +4527,7 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 
	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);



	mutex_lock(&adev->srbm_mutex);

	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {

	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {

		nv_grbm_select(adev, 0, 0, 0, i);

		/* CP and shaders */

		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
@@ -4540,7 +4538,7 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 


	/* Initialize all compute VMIDs to have no GDS, GWS, or OA

	   acccess. These should be enabled by FW for target VMIDs. */

	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {

	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {

		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);

		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);

		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);