Commit 409af447 authored by Jessica Zhang's avatar Jessica Zhang Committed by Rob Clark
Browse files

drm/msm/dsi: fix wrong type in msm_dsi_host 



Change byte_clk_rate, pixel_clk_rate, esc_clk_rate, and src_clk_rate
from u32 to unsigned long, since clk_get_rate() returns an unsigned long.

Fixes: a6bcddbc ("drm/msm: dsi: Handle dual-channel for 6G as well")
Reported-by: default avatarDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: default avatarJessica Zhang <jesszhan@codeaurora.org>
Link: https://lore.kernel.org/r/20211020183438.32263-1-jesszhan@codeaurora.org


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 8bf71a57

drivers/gpu/drm/msm/dsi/dsi_host.c

+12 −12
Original line number Diff line number Diff line
@@ -116,16 +116,16 @@ struct msm_dsi_host { 
	struct clk *pixel_clk_src;

	struct clk *byte_intf_clk;



	u32 byte_clk_rate;

	u32 pixel_clk_rate;

	u32 esc_clk_rate;

	unsigned long byte_clk_rate;

	unsigned long pixel_clk_rate;

	unsigned long esc_clk_rate;



	/* DSI v2 specific clocks */

	struct clk *src_clk;

	struct clk *esc_clk_src;

	struct clk *dsi_clk_src;



	u32 src_clk_rate;

	unsigned long src_clk_rate;



	struct gpio_desc *disp_en_gpio;

	struct gpio_desc *te_gpio;
@@ -463,10 +463,10 @@ int msm_dsi_runtime_resume(struct device *dev) 


int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)

{

	u32 byte_intf_rate;

	unsigned long byte_intf_rate;

	int ret;



	DBG("Set clk rates: pclk=%d, byteclk=%d",

	DBG("Set clk rates: pclk=%d, byteclk=%lu",

		msm_host->mode->clock, msm_host->byte_clk_rate);



	ret = dev_pm_opp_set_rate(&msm_host->pdev->dev,
@@ -546,7 +546,7 @@ int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) 
{

	int ret;



	DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d",

	DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu",

		msm_host->mode->clock, msm_host->byte_clk_rate,

		msm_host->esc_clk_rate, msm_host->src_clk_rate);
@@ -635,10 +635,10 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 
	clk_disable_unprepare(msm_host->byte_clk);

}



static u32 dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_bonded_dsi)

static unsigned long dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_bonded_dsi)

{

	struct drm_display_mode *mode = msm_host->mode;

	u32 pclk_rate;

	unsigned long pclk_rate;



	pclk_rate = mode->clock * 1000;
@@ -658,7 +658,7 @@ static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 
{

	u8 lanes = msm_host->lanes;

	u32 bpp = dsi_get_bpp(msm_host->format);

	u32 pclk_rate = dsi_get_pclk_rate(msm_host, is_bonded_dsi);

	unsigned long pclk_rate = dsi_get_pclk_rate(msm_host, is_bonded_dsi);

	u64 pclk_bpp = (u64)pclk_rate * bpp;



	if (lanes == 0) {
@@ -675,7 +675,7 @@ static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 
	msm_host->pixel_clk_rate = pclk_rate;

	msm_host->byte_clk_rate = pclk_bpp;



	DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,

	DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate,

				msm_host->byte_clk_rate);



}
@@ -734,7 +734,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 


	msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;



	DBG("esc=%d, src=%d", msm_host->esc_clk_rate,

	DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate,

		msm_host->src_clk_rate);



	return 0;